Inventor

ADILETTA MATTHEW J

US120 patents

⚠️ This page may combine multiple inventors who share the name “ADILETTA MATTHEW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADILETTA MATTHEW J

INTEL CORP

Microengine for parallel processor architecture

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode

Arbitrating command requests in a parallel multi-threaded processing system

Technologies for optical communication in rack clusters

Techniques to process packets in a dual-mode switching environment

Technologies for cooling rack mounted sleds

Robotically serviceable computing rack and sleds

Technologies for providing power to a rack

Technologies for sled architecture

Technologies for optical communication in rack clusters

Register set used in multithreaded parallel processor architecture

SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues

Mapping requests from a processing unit that uses memory-mapped input-output space

Read lock miss control and queue management

Journaling for parallel hardware threads in multithreaded processor

Thread signaling in multi-threaded network processor

Parallel multi-threaded processing

Communication between processors

Handling contiguous memory references in a multi-queue system

SRAM controller for parallel processor architecture including address and command queue and arbiter

Read lock miss control and queue management

Technologies for rack architecture

SDRAM controller for parallel processor architecture

Multi-threaded sequenced receive for fast network port stream of packets

Multi-threaded sequenced transmit software for packet forwarding device

Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section

Memory shared between processing threads

Optimizations to receive packet status from fifo bus

Solving parallel problems employing hardware multi-threading in a parallel processing environment

Thread signaling in multi-threaded processor

Techniques for generating a routing table for a mesh network having ad hoc connections

Robotically serviceable computing rack and sleds

Technologies for blind mating for sled-rack connections

Method and apparatus for gigabit packet assignment for multithreaded packet processing

Multi-threaded round-robin receive for fast network port

Multi-threaded sequenced receive for fast network port stream of packets

Memory interleaving

Communication between processors

Control mechanisms for enqueue and dequeue operations in a pipelined network processor

Microengine for parallel processor architecture

Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch

Bus interface with a first-in-first-out memory

Communication between processors

Method for memory allocation and management using push/pop apparatus

Displaying information relating to a logic design

DIGITAL EQUIPMENT CORP

Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition storage and retrieval

Method and apparatus for performing fast division

Apparatus for performing fast multiplication

COMPAQ COMPUTER CORP

Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition, storage and retrieval