Inventor

VAN HUBEN GARY A

US50 patents

⚠️ This page may combine multiple inventors who share the name “VAN HUBEN GARY A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN HUBEN GARY A

IBM

Efficient calibration of a data eye for memory devices

Modular scalable system for managing data in a heterogeneous environment with generic structure for control repository access transactions

Data management interoperability methods for heterogeneous directory structures

Methods for shared data management in a pervasive computing environment

High speed remote storage controller

Clustered computer system with deadlock avoidance

Efficient calibration of memory devices

Test and bring-up of an enhanced cascade interconnect memory system

Method for the creation of a hybrid cycle simulation model

Bus protocol for a switchless distributed shared memory computer system

Method for deadlock avoidance in a cluster environment

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Efficient calibration of a data eye for memory devices

Synchronization and order detection in a memory system

Method for replicating and synchronizing a plurality of physical instances with a logical master

Distributed shared resource management

Dual asynchronous and synchronous memory system

Dual asynchronous and synchronous memory system

Software entity for the creation of a hybrid cycle simulation model

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Efficient calibration of a data eye for memory devices

Partial data replay in a distributed memory buffer system

Efficient calibration of a data eye for memory devices

Efficient calibration of memory devices

Synchronization and order detection in a memory system

Programmable bus driver launch delay/cycle delay to reduce elastic interface elasticity requirements

Method, system, and program product for automated verification of gating logic using formal verification

Simultaneous write and read calibration of an interface within a circuit

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Address/command chip controlled data chip address sequencing for a distributed memory buffer system

Reducing latency of memory read operations returning data on a read data path across multiple clock boundaries, to a host implementing a high speed serial interface

Address/command chip synchronized autonomous data chip address sequencer for a distributed buffer memory system

Method, system, and program product for automated verification of gating logic using formal verification

Host synchronized autonomous data chip address sequencer for a distributed buffer memory system

Partial data replay in a distributed memory buffer system

Double data rate (DDR) memory read latency reduction

Synchronization and order detection in a memory system

Cross-layer power optimization of program code and/or software architecture

Simultaneous write, read, and command-address-control calibration of an interface within a circuit

Physically aware test patterns in semiconductor fabrication

Physically aware test patterns in semiconductor fabrication

Packeted protocol device test system

JTAG support over a broadcast bus in a distributed memory buffer system

Host controlled data chip address sequencing for a distributed memory buffer system

Reducing chip latency at a clock boundary by reference clock phase adjustment

Register access in a distributed memory buffer system

HNATKO STEVEN J

System and method for a hierarchical buffer system for a shared data bus

Hierarchical buffer system enabling precise data delivery through an asynchronous boundary