Inventor

CHI CHENG

CN77 patents

⚠️ This page may combine multiple inventors who share the name “CHI CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHI CHENG

IBM

Uniform bottom spacers in vertical field effect transistors

Metal layer tip to tip short

Two-dimensional self-aligned super via integration on self-aligned gate contact

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

Vertical field effect transistors with self aligned gate and source/drain contacts

Nanosheet transistor with robust source/drain isolation from substrate

Method and apparatus of fabricating source and drain epitaxy for vertical field effect transistor

Techniques for VFET top source/drain epitaxy

Forming a combination of long channel devices and vertical transport fin field effect transistors on the same substrate

Via formation using sidewall image transfer process to define lateral dimension

Graphoepitaxy directed self assembly

Via formation using sidewall image transfer process to define lateral dimension

Decoupling capacitor inside gate cut trench

Phase-change memory device with reduced programming voltage

Gate contact over active region with self-aligned source/drain contact

Nanosheet transistor with robust source/drain isolation from substrate

Two-dimensional self-aligned super via integration on self-aligned gate contact

Self-aligned single dummy fin cut with tight pitch

Self-aligned finFET formation

Uniform bottom spacer for vertical field effect transistor

Self-aligned single dummy fin cut with tight pitch

Two-dimensional self-aligned super via integration on self-aligned gate contact

Graphoepitaxy directed self assembly

Machine learning for computational patterning

Random weight initialization of non-volatile memory array

Ferroelectric and paraelectric stack capacitors

Gate contact inside gate cut trench

Field effect transistor (FET) devices

Low capacitance low RC wrap-around-contact

Resistive switching memory cell

Resistive switching memory cell

NCFETS with complimentary capacitance matching using stacked n-type and p-type nanosheets

Vertical resistive memory device with embedded selectors

Self-aligned top via structure

Nanosheet devices with improved electrostatic integrity

Uniform bottom spacer for VFET devices

Method for fin formation with a self-aligned directed self-assembly process and cut-last scheme

Decoupling capacitor inside gate cut trench

Multilayer dielectric for metal-insulator-metal capacitor

Resistance drift mitigation in non-volatile memory cell

GLOBALFOUNDRIES INC

Nanosheet devices with CMOS epitaxy and method of forming

Nanosheet devices with CMOS epitaxy and method of forming

Method of concurrently forming source/drain and gate contacts and related device

Method of concurrently forming source/drain and gate contacts and related device

BEIJING KUAIMAJIABIAN TECHNOLOGY CO LTD

Display screen or portion thereof with a graphical user interface

Display screen or portion thereof with a graphical user interface

VERISILICON MICROELECTRONICS SHANGHAI CO LTD

Tessellation data processing method, system, medium and vector graphics processing device

NEUSOFT CORP

Method, device and apparatus for planning vehicle speed

GLOBALFOUNDRIES US INC

Gate contact structure for a transistor device

BEIJING BYTEDANCE NETWORK TECH CO LTD

Live streaming interface interaction method and apparatus, electronic device, and computer-readable medium