Inventor

HUANG PO-HSIANG

TW134 patents

⚠️ This page may combine multiple inventors who share the name “HUANG PO-HSIANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HUANG PO-HSIANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

Layout design methodology for stacked devices

Method for generating layout diagram including cell having pin patterns and semiconductor device based on same

Method for generating layout diagram including protruding pin cell regions and semiconductor device based on same

Second semiconductor wafer attached to a first semiconductor wafer with a through hole connected to an inductor

Integrated circuit, system for and method of forming an integrated circuit

Power gating for three dimensional integrated circuits (3DIC)

Method of modifying cell and global connection routing method

Integrated circuit having a high cell density

Package structure and method for forming the same

Info packages including thermal dissipation blocks

Barrier free interface between beol interconnects

Semiconductor device having fuse array and method of making the same

Inter-wire cavity for low capacitance

Integrated circuit fin structure manufacturing method

Layout design methodology for stacked devices

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

Pin modification for standard cells

Method for manufacturing a cell having pins and semiconductor device based on same

Heat dissipation structure including stacked chips surrounded by thermal interface material rings

Electromagnetic shielding metal-insulator-metal capacitor structure

Integrated circuit fin layout method, system, and structure

Integrated circuit including a first semiconductor wafer and a second semiconductor wafer, semiconductor device including a first semiconductor wafer and a second semiconductor wafer and method of manufacturing same

Pin modification for standard cells

Integrated circuit device with improved layout

Method of fabricating integrated circuit having staggered conductive features

Integrated circuit structure

Standard cells and variations thereof within a standard cell library

Electromagnetic shielding metal-insulator-metal capacitor structure

Pin modification for standard cells

Placement constraint method for multiple patterning of cell-based chip design

Integrated circuit layout methods, structures, and systems

Integrated circuit having staggered conductive features

Method and system for pin layout

Power gating for three dimensional integrated circuits (3DIC)

Interconnect structure and method for forming the same

Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit

Interconnect structure, semiconductor structure including interconnect structure and method for forming the same

Semiconductor device and method of manufacture

Cell structures and semiconductor devices having same

Semiconductor device having fuse array and method of making the same

Semiconductor device with filler cell region, method of generating layout diagram and system for same

Cell structures and semiconductor devices having same

Circuit with combined cells and method for manufacturing the same

Semiconductor package having an encapsulant comprising conductive fillers and method of manufacture

Integrated circuit and method of generating integrated circuit layout

TAIWAN SEMICONDUCTOR MFG

System and method for across-chip thermal and power management in stacked IC designs

Power gating for three dimensional integrated circuits (3DIC)

Method of making a semiconductor device including barrier layers for copper interconnect

LIU NAI-WEI

Barrier layers for copper interconnect