Inventor

COTE JEAN-FRANCOIS

US40 patents

⚠️ This page may combine multiple inventors who share the name “COTE JEAN-FRANCOIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

COTE JEAN-FRANCOIS

LOGICVISION INC

Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same

Method and circuit for collecting memory failure information

Scan test method for providing real time identification of failing test patterns and test bist controller for use therewith

Method and apparatus for testing high performance circuits

Test access circuit and method of accessing embedded test controllers in integrated circuit modules

Clock skew management method and apparatus

Asynchronous interface

Method for at-speed testing of memory interface using scan

Clock controller for at-speed testing of scan circuits

Method for scan testing of digital circuit, digital circuit for use therewith and program product for incorporating test methodology into circuit description

Method and program product for completing a circuit design having embedded test structures

Method and apparatus for controlling power level during BIST

Method and apparatus for scan testing digital circuits

Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby

Self-contained embedded test design environment and environment setup utility

Method and program product for designing hierarchical circuit for quiescent current testing and circuit produced thereby

Method for collecting failure information for a memory using an embedded test controller

Method and circuitry for controlling clocks of embedded blocks during logic bist test mode

Verification of embedded test structures in circuit designs

Clocking methodology for at-speed testing of scan circuits with synchronous clocks

MENTOR GRAPHICS CORP

Method and apparatus for storing and distributing memory repair information

Data generation for streaming networks in circuits

Data streaming for testing identical circuit blocks

Test access architecture for multi-die circuits

Test access architecture for stacked dies

Clock gating and scan clock generation for circuit test

Local clock injection and independent capture for circuit test of multiple cores in clock mesh architecture

Efficient and flexible network for streaming data in circuits

Streaming networks efficiency using data throttling

LOGIC VISION INC

Method and apparatus for high-speed interconnect testing

Fault insertion method, boundary scan cells, and integrated circuit for use therewith

Method and apparatus for testing multi-port memory

Method and apparatus for testing multi-port memory using shadow read

SIEMENS IND SOFTWARE INC

Asynchronous interface for transporting test-related data via serial channels

Multi-capture at-speed scan test based on a slow clock signal

High bandwidth IJTAG through high speed parallel bus

MATROX GRAPHICS INC

Efficient video processing method and system

Motion compensation using shared resources of a graphics processor unit

COTE JEAN-FRANCOIS

Efficient execution of color space processing functions in a graphics processing unit

NADEAU-DOSTIE BENOIT

Methods for at-speed testing of memory interface