Inventor

PARAMESWARAN HARINDRANATH

IN9 patents

⚠️ This page may combine multiple inventors who share the name “PARAMESWARAN HARINDRANATH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YU HENRY

2 patents

US9064063B1Jun 23, 2015

Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraints

YU HENRY13 citations81

US8694943B1Apr 8, 2014

Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awareness

YU HENRY4 citations70

CADENCE DESIGN SYSTEMS INC

2 patents

US9026958B1May 5, 2015

Method and system for double patterning technology (DPT) odd loop visualization for an integrated circuit layout

CADENCE DESIGN SYSTEMS INC6 citations72

US8839183B2Sep 16, 2014

Method and apparatus for derived layers visualization and debugging

CADENCE DESIGN SYSTEMS INC0 citations43

SHRIVASTAVA SACHIN

2 patents

US8086983B2Dec 27, 2011

Method and system for performing improved timing window analysis

SHRIVASTAVA SACHIN5 citations58

US8612199B2Dec 17, 2013

Netlist partitioning for characterizing effect of within-die variations

SHRIVASTAVA SACHIN1 citations47

PARAMESWARAN HARINDRANATH

1 patent

US8813006B1Aug 19, 2014

Accelerated characterization of circuits for within-die process variations

PARAMESWARAN HARINDRANATH13 citations78

MAJUMDER CHAYAN

1 patent

US8711177B1Apr 29, 2014

Generation, display, and manipulation of measurements in computer graphical designs

MAJUMDER CHAYAN2 citations61

JUNEJA PARDEEP

1 patent

US8555237B1Oct 8, 2013

Method and apparatus for design rule violation reporting and visualization

JUNEJA PARDEEP6 citations60