Inventor

FAVOR JOHN G

US120 patents

⚠️ This page may combine multiple inventors who share the name “FAVOR JOHN G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAVOR JOHN G

ADVANCED MICRO DEVICES INC

RISC86 instruction set

System and method for conditional moving an operand from a source register to destination register

Flexible implementation of a system management mode (SMM) in a processor

Flexible implementation of a system management mode (SMM) in a processor

Prefetch instruction mechanism for processor

Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay

Unified multi-function operation scheduler for out-of-order execution in a superscaler processor

Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device

Decoding operands for multimedia applications instruction coded with less number of bits than combination of register slots and selectable specific values

RISC86 instruction set

Unified multi-function operation scheduler for out-of-order execution in a superscalar processor

Instruction predecode and multiple instruction decode

Instruction decoder including emulation using indirect specifiers

Integration of multi-stage execution units with a scheduler for single-stage execution units

Branch prediction device with two levels of branch prediction cache

Microprocessor including multiple register files mapped to the same logical storage and inhibiting sychronization between the register files responsive to inclusion of an instruction in an instruction sequence

Method for reducing number of bits used in storage of instruction address pointer values

Branch prediction device with two levels of branch prediction cache

Instruction buffer organization method and system

Scan chains for out-of-order load/store execution control

Self-modifying code handling system

Out-of-order load/store execution control

Scan chain for rapidly identifying first or second objects of selected types in a sequential list

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

NEXGEN MICROSYSTEMS

Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence

Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

Two-level branch prediction cache

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

Two-level branch prediction cache

Integrated single structure branch prediction cache

COMPAQ COMPUTER CORP

System and method for conditionally moving an operand from a source register to a destination register

Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage

System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot

Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle

Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot

REDBACK NETWORKS INC

Cache retry request queue

Method and apparatus for out-of-order processing of packets using linked lists

Decoding suffix instruction specifying replacement destination for primary instruction

Method and apparatus for out-of-order processing of packets

Method and apparatus for implementing a switching unit including a bypass path

VENTANA MICRO SYSTEMS INC

Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions

Single cycle predictor

Microprocessor with prediction unit pipeline that provides a next fetch address at a rate of one per clock cycle

Processor that prevents speculative execution across translation context change boundaries to mitigate side channel attacks

NEXGEN INC

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts

Two-level branch prediction cache

Method an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency

COMPAQ COMPUTER CORP AND ADVAN

Computer modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instruction cycles

ERICSSON AB

Method and apparatus for out-of-order processing of packets using linked lists

ORACLE AMERICA INC

Maintaining memory coherency with a trace cache