Inventor

SRINIVASAN SRIVATSAN

US53 patents

⚠️ This page may combine multiple inventors who share the name “SRINIVASAN SRIVATSAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SRINIVASAN SRIVATSAN

VENTANA MICRO SYSTEMS INC

Translation lookaside buffer consistency directory for use with virtually-indexed virtually-tagged first level data cache that holds page table permissions

Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction

Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache

Microprocessor that prevents same address load-load ordering violations

Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries

Store-to-load forwarding correctness checks at store instruction commit

Generational physical address proxies

Write combining using physical address proxies stored in a write combine buffer

Physical address proxy reuse management

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Physical address proxy (PAP) residency determination for reduction of PAP reuse

Using physical address proxies to accomplish penalty-less processing of load/store instructions whose data straddles cache line address boundaries

Virtually-indexed cache coherency using physical address proxies

Store-to-load forwarding correctness checks at store instruction commit

Unforwardable load instruction re-execution eligibility based on cache update by identified store instruction

Using physical address proxies to handle synonyms when writing store data to a virtually-indexed cache

Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context

Physical address proxy reuse management

Conditioning store-to-load forwarding (STLF) on past observations of STLF propriety

Processor that mitigates side channel attacks by preventing cache memory state from being affected by a missing load operation by inhibiting or canceling a fill request of the load operation if an older load generates a need for an architectural exception

Processor that mitigates side channel attacks by prevents cache line data implicated by a missing load address from being filled into a data cache memory when the load address specifies a location with no valid address translation or no permission to read from the location

Physically-tagged data cache memory that uses translation context to reduce likelihood that entries allocated during execution under one translation context are accessible during execution under another translation context

Hardware cache coherency using physical address proxies

Store-to-load forwarding using physical address proxies to identify candidate set of store queue entries

Power management of devices with differentiated power scaling based on relative power benefit estimation

Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries

Microprocessor that prevents same address load-load ordering violations using physical address proxies

Virtually-indexed cache coherency using physical address proxies

Store-to-load forwarding correctness checks using physical address proxies stored in load queue entries

Non-cacheable access handling in processor with virtually-tagged virtually-indexed data cache

Thwarting store-to-load forwarding side channel attacks by pre-forwarding matching of physical address proxies and/or permission checking

Processor that mitigates side channel attacks by preventing all dependent instructions from consuming architectural register result produced by instruction that causes a need for an architectural exception

Physical address proxy (PAP) residency determination for reduction of PAP reuse

Processor that mitigates side channel attacks by expeditiously initiating flushing of instructions dependent upon a load instruction that causes a need for an architectural exception

Processor that mitigates side channel attacks by providing random load data as a result of execution of a load operation that does not have permission to access a load address

Virtually-tagged data cache memory that uses translation context to make entries allocated during execution under one translation context inaccessible during execution under another translation context

Store-to-load forwarding using physical address proxies stored in store queue entries

R SOFTWARE INC

Application programming interface scoring, ranking and selection

Processing a query having calls to multiple data sources

Public and private API hub synchronization

Processing a query having calls to multiple data sources

NETLOGIC MICROSYSTEMS INC

System and method for performing a register renaming operation utilizing hardware which is capable of operating in at least two modes utilizing registers of multiple widths

Universal branch identifier for invalidation of speculative instructions

OPTUM INC

Priority-driven federated query-based data caching

Dynamically tailored time intervals for federated query system

VONAGE BUSINESS INC

Systems and methods for providing call verification

Systems and methods for providing call verification

SINGH GAURAV

Age matrix for queue entries dispatch order

UNIV TEXAS

System, method and apparatus for allocating hardware resources using pseudorandom sequences