Inventor

LIU YEN-CHENG

US85 patents

⚠️ This page may combine multiple inventors who share the name “LIU YEN-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU YEN-CHENG

INTEL CORP

High performance interconnect

Method and apparatus to dynamically adjust resource power usage in a distributed system

Method and apparatus for dynamically controlling power management in a distributed system

High performance interconnect

Remote atomic operations in multi-socket systems

Speculative reads in buffered memory

Two level memory full line writes

Providing common caching agent for core and integrated input/output (IO) module

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

Method, system, and apparatus for a core activity detector to facilitate dynamic power management in a distributed system

High performance interconnect

High performance interconnect

Multiple dies hardware processors and methods

Method and apparatus for cache line write back operation

Remote atomic operations in multi-socket systems

Virtual shared cache mechanism in a processing device

Method and apparatus for store durability and ordering in a persistent memory architecture

High performance interconnect

High performance interconnect

Spatial and temporal merging of remote atomic operations

Flexible on-die fabric interface

Multiple dies hardware processors and methods

Preventing system snoop and cross-snoop conflicts

Method, apparatus and system for modular on-die coherent interconnect for packetized communication

Enforcing global ordering through a caching bridge in a multicore multiprocessor system

Remote atomic operations in multi-socket systems

Processor and method implementing a cacheline demote machine instruction

Spatial and temporal merging of remote atomic operations

Optimizing power usage by factoring processor architectural events to PMU

Virtual retry queue

Optimizing power usage by factoring processor architectural events to PMU

Multiple dies hardware processors and methods

TRIFO INC

Autonomous platform guidance systems with unknown environment mapping

Autonomous platform guidance systems with auxiliary sensors and obstacle avoidance

Autonomous platform guidance systems with auxiliary sensors and task planning

Autonomous platform guidance systems with task planning and obstacle avoidance

Autonomous platform guidance systems with unknown environment mapping

Autonomous platform guidance systems with task planning and obstacle avoidance

LIU YEN-CHENG

Optimizing power usage by processor cores based on architectural events

Providing common caching agent for core and integrated input/output (IO) module

Optimizing power usage by processor cores based on architectural events

MEDIATEK INC

Broadcast channel enhancement with polar code

Polar bit allocation for partial content extraction

Polar bit allocation for partial content extraction

YIGZAW THEODROS

Injecting a data error into a writeback path to memory

BLANKENSHIP ROBERT G

Ring protocol for low latency interconnect switch

MEDIATEK SINGAPORE PTE LTD

Large-scale fading coefficient estimation in wireless massive MIMO systems

INTEL CORPORAITON

System, apparatus and method for increasing bandwidth of edge-located agents of an integrated circuit

CAI ZHONG-NING

Cache coherency sequencing implementation and adaptive LLC access priority control for CMP

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductive structure and manufacturing method thereof