Inventor

BI ZHENXING

US181 patents

⚠️ This page may combine multiple inventors who share the name “BI ZHENXING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BI ZHENXING

IBM

Buffer regions for blocking unwanted diffusion in nanosheet transistors

Closely packed vertical transistors with reduced contact resistance

Vertically stacked nanosheet CMOS transistor

Tunnel transistor

Vertical transport Fin field effect transistors on a substrate with varying effective gate lengths

Vertical silicon/silicon-germanium transistors with multiple threshold voltages

Hybrid-channel nano-sheet FETs

Method and structure for improving vertical transistor

Forming on-chip metal-insulator-semiconductor capacitor

Approach to minimization of strain loss in strained fin field effect transistors

Vertical transport FET devices with uniform bottom spacer

Vertical FET symmetric and asymmetric source/drain formation

Transistor with asymmetric spacers

Method and structure for forming vertical transistors with shared gates and separate gates

Hybridization fin reveal for uniform fin reveal depth across different fin pitches

Vertically stacked nanosheet CMOS transistor

Gate-all-around field-effect transistor devices having source/drain extension contacts to channel layers for reduced parasitic resistance

Producing strained nanosheet field effect transistors using a phase change material

Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

Vertical FET transistor with reduced source/drain contact resistance

Isolation structure for stacked vertical transistors

Nanosheet FET bottom isolation

Integration scheme for non-volatile memory on gate-all-around structure

Hybrid-channel nano-sheet FETs

Bottom isolation for nanosheet transistors on bulk substrate

Nanosheet CMOS transistors

Transistor with asymmetric source/drain overlap

Vertical transistors with multiple gate lengths

Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors

Resistor fins

Transistor with improved air spacer

FinFET with uniform shallow trench isolation recess

Asymmetrical vertical transistor

Forming a fin cut in a hardmask

Stacked nanowires

Fin type field effect transistors with different pitches and substantially uniform fin reveal

Nanosheet capacitor

Polysilicon residue removal in nanosheet MOSFETs

Low undercut N-P work function metal patterning in nanosheet replacement metal gate process

Shallow trench isolation recess process flow for vertical field effect transistor fabrication

Source and drain epitaxy and isolation for gate structures

Approach to bottom dielectric isolation for vertical transport fin field effect transistors

Field effect transistor devices with self-aligned source/drain contacts and gate contacts positioned over active transistors

Nanosheet transistor having a strained channel with strain-preserving multi-segmented source/drain regions

Stacked nanosheet complementary metal oxide semiconductor field effect transistor devices

Closely packed vertical transistors with reduced contact resistance

Self-aligned fin recesses in nanosheet field effect transistors

Nanosheet transistor bottom isolation

Gate spacer and inner spacer formation for nanosheet transistors having relatively small space between gates

TESSERA LLC

Hybrid-channel nano-sheet FETs