Inventor

PRATHER MATTHEW A

US77 patents

⚠️ This page may combine multiple inventors who share the name “PRATHER MATTHEW A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PRATHER MATTHEW A

MICRON TECHNOLOGY INC

Methods for error count reporting with scaled error count information, and memory devices employing the same

Error correction in row hammer mitigation and target row refresh

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Error check and scrub for semiconductor memory device

Error correction in row hammer mitigation and target row refresh

Error check and scrub for semiconductor memory device

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Individually addressing memory devices disconnected from a data bus

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Methods for on-die memory termination and memory devices and systems employing the same

Memory devices configured to provide external regulated voltages

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Memory module multiple port buffer techniques

Refresh operation in multi-die memory

Background operations in memory

Error correction in row hammer mitigation and target row refresh

Methods for on-die memory termination and memory devices and systems employing the same

Individually addressing memory devices disconnected from a data bus

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Refresh operation in multi-die memory

Individually addressing memory devices disconnected from a data bus

Methods for on-die memory termination and memory devices and systems employing the same

Memory mapping using commands to transfer data and/or perform logic operations

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Individually addressing memory devices disconnected from a data bus

Memory devices configured to provide external regulated voltages

Apparatuses and methods for configuring I/OS of memory for hybrid memory modules

Memory devices with programmable latencies and methods for operating the same

Methods of synchronizing memory operations and memory systems employing the same

Combined memory module logic devices for reduced cost and improved functionality

Power management in memory

Command bus in memory

Techniques for power management using loopback

Memory devices configured to provide external regulated voltages

Memory mapping for memory, memory modules, and non-volatile memory

Dual speed memory

Methods for on-die memory termination and memory devices and systems employing the same

Memory mapping using commands to transfer data and/or perform logic operations

Command bus in memory

Techniques for power management using loopback

LODESTAR LICENSING GROUP LLC

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Error check and scrub for semiconductor memory device

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices configured to provide external regulated voltages

Techniques for power management using loopback

Individually addressing memory devices disconnected from a data bus

Refresh operation in multi-die memory

Apparatuses and methods for configuring I/Os of memory for hybrid memory modules

Background operations in memory

Memory mapping for memory, memory modules, and non-volatile memory