Inventor

ROONEY RANDALL J

US39 patents

⚠️ This page may combine multiple inventors who share the name “ROONEY RANDALL J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROONEY RANDALL J

MICRON TECHNOLOGY INC

Methods for row hammer mitigation and memory devices and systems employing the same

Methods for error count reporting with scaled error count information, and memory devices employing the same

Error correction in row hammer mitigation and target row refresh

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Error check and scrub for semiconductor memory device

Error correction in row hammer mitigation and target row refresh

Error check and scrub for semiconductor memory device

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory module multiple port buffer techniques

Error correction in row hammer mitigation and target row refresh

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Memory devices and systems configured to communicate a delay signal and methods for operating the same

Reserved rows for row-copy operations for semiconductor memory devices and associated methods and systems

Memory with deterministic worst-case row address servicing, and associated systems, devices, and methods

Error correcting code poisoning for memory devices and associated methods and systems

Memory devices and systems configured to communicate a delay signal and methods for operating the same

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Generating test data for a memory system design based on operation of a test system, and related methods, devices, and systems

Methods for error count reporting with scaled error count information, and memory devices employing the same

Memory device on-die ECC data

Word line characteristics monitors for memory devices and associated methods and systems

Error correcting code poisoning for memory devices and associated methods and systems

Reserved rows for row-copy operations for semiconductor memory devices and associated methods and systems

Word line characteristics monitors for memory devices and associated methods and systems

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Normalization of detecting and reporting failures for a memory device

Memory module multiple port buffer techniques

Error injection methods using soft post-package repair (sPPR) techniques and memory devices and memory systems employing the same

LODESTAR LICENSING GROUP LLC

Error check and scrub for semiconductor memory device

Methods for row hammer mitigation and memory devices and systems employing the same

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Methods for providing device status in response to read commands directed to write-only mode register bits and memory devices and systems employing the same

Methods for performing multiple memory operations in response to a single command and memory devices and systems employing the same

Methods for error count reporting with scaled error count information, and memory devices employing the same

Methods for row hammer mitigation and memory devices and systems employing the same

Methods for error count reporting with scaled error count information, and memory devices employing the same

Normalization of detecting and reporting failures for a memory device