Inventor

CHIANG KUO-CHENG

TW392 patents

⚠️ This page may combine multiple inventors who share the name “CHIANG KUO-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIANG KUO-CHENG

TAIWAN SEMICONDUCTOR MFG CO LTD

Capacitance reduction for back-side power rail device

Multi-gate device and related methods

Devices including gate spacer with gap or void and methods of forming the same

Gate isolation for multigate device

Semiconductor structures and methods thereof

Tuning threshold voltage in nanosheet transitor devices

Semiconductor device structure

Gate patterning process for multi-gate devices

Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench

Semiconductor devices with backside power rail and backside self-aligned via

Uniform gate width for nanostructure devices

Multi-gate device and related methods

Backside power rail structure and methods of forming same

Self-aligned structure for semiconductor devices

Buried power rail and method forming same

Gap-insulated semiconductor device

Semiconductor device having nanosheet transistor and methods of fabrication thereof

Semiconductor device with backside self-aligned power rail and methods of forming the same

Input/output semiconductor devices

Semiconductor device with dummy fin and liner and method of forming the same

Fin structures having varied fin heights for semiconductor device

Silicon and silicon germanium nanowire formation

Mixed workfunction metal for nanosheet device

Dual channel gate all around transistor device and fabrication methods thereof

Stacked gate-all-around FinFET and method forming the same

Semiconductor device structure and methods of forming the same

Gate isolation for multigate device

Seam free isolation structures and method for making the same

Capacitance reduction for back-side power rail device

Gate-all-around field-effect transistor device

Gate isolation structure

Uniform gate width for nanostructure devices

Integration of silicon channel nanostructures and silicon-germanium channel nanostructures

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

Semiconductor device fabrication methods and structures thereof

Transistor including downward extending silicide

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

Fin-based semiconductor device structure including self-aligned contacts and method for forming the same

Gate-all-around devices having self-aligned capping between channel and backside power rail

Nanosheet device architecture for cell-height scaling

Field effect transistor with fin isolation structure and method

Semiconductor structure and method for forming the same

Semiconductor device structure and methods of forming the same

Multi-layer channel structures and methods of fabricating the same in field-effect transistors preliminary class

Self-aligned metal gate for multigate device

Semiconductor devices with backside power rail and backside self-aligned via

Gap-insulated semiconductor device

Semiconductor device fabrication methods and structures thereof

Semiconductor device structure and methods of forming the same

TU KUO-CHI

Structure for protecting metal-insulator-metal capacitor in memory device from charge damage