Inventor

TERNULLO JR LUIGI

US28 patents

⚠️ This page may combine multiple inventors who share the name “TERNULLO JR LUIGI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TERNULLO JR LUIGI

IBM

Memory array built-in self test circuit for testing multi-port memory arrays

Built-in self-test for logic circuitry at memory array output

BIST tester for multiple memories

Field effect transistor having contact layer of transistor gate electrode material

Testing logic associated with numerous memory cells in the word or bit dimension in parallel

Method and apparatus for achieving higher performance data compression in ABIST testing by reducing the number of data outputs

Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor

Field effect transistor having contact layer of transistor gate electrode material

Semiconductor structures which incorporate thin film transistors

Using one memory to supply addresses to an associated memory during testing

Memory array built-in self-test circuit having a programmable pattern generator for allowing unique read/write operations to adjacent memory cells, and method therefor

Method and apparatus to determine erroneous value in memory cells using data compression

Rapid compare of two binary numbers

Method and apparatus for output deselecting of data during test

Method and apparatus for testing differential signals

VANGUARD INT SEMICONDUCT CORP

Multiple data clock activation with programmable delay for use in multiple CAS latency memory devices

Timing circuit that selectively triggers on a rising or falling input signal edge

Self-refresh test time reduction scheme

Internal charge pump voltage limit control

High-speed synchronous write control scheme

Regulator system for an on-chip supply voltage generator

Local bit switch decode circuit and method

On-chip-generated supply voltage regulator with power-up mode

Method and circuit for disabling a two-phase charge pump

Dynamically adjustable on-chip supply voltage generation

Crow-bar current reduction circuit

Semiconductor memory device with improved read signal generation of data lines and assisted precharge to mid-level

PALOMAR TECHN CORP

Method of fabricating an ultra-high resolution three-color screen