Inventor

GUPTA LALIT

US50 patents

⚠️ This page may combine multiple inventors who share the name “GUPTA LALIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUPTA LALIT

ADVANCED RISC MACH LTD

System device and method for providing single port memory access in bitcell array by tracking dummy wordline

Integrated circuit using discharging circuitries for bit lines

Dummy wordline tracking circuitry

SRAM architecture with bitcells of varying speed and density

Redundancy schemes for memory cell repair

Dummy wordline design techniques

Write assist circuitry

Write assist circuitry

Memory power-gating techniques

Pulse stretcher circuitry

Memory power-gating techniques

Concurrent memory access operations

Circuit architecture to derive higher mux from lower mux design

Column multiplexer circuitry

Column multiplexer circuitry

Level shifter with isolation logic

Concurrent access techniques utilizing wordlines with the same row address in single port memory

Pulse stretcher circuitry

Power-on-reset circuit

Power-on-reset circuit

Configurable multiplexing circuitry

Coupling compensation circuitry

Dummy bitline circuitry

Coupling compensation circuitry

High-speed memory architecture

Circuits and methods for capacitor modulation

Providing a discharge boundary using bitline discharge control circuitry for an integrated circuit

DSILO INC

Database query generation using natural language text

Database query generation using natural language text

Self-executing protocol generation from natural language text

Database generation from natural language text documents

Database generation from natural language text documents

Self-executing protocol generation from natural language text

Database query generation using natural language text

Database generation from natural language text documents

NVIDIA CORP

Level-shifter having a wide operating range, a fast output fall delay and improved rise time

Keeper-free volatile memory system

Area efficient memory cell read disturb mitigation

Slew signal shaper circuit using two signal paths

Contention-free dual-voltage logic cell

Multi-voltage RAM used to cross clock and voltage domains

Shared metal wire capacitance for negative bit-line

KONINKLIJKE PHILIPS NV

Automatic blood vessel identification by name

Excitation schemes for low-cost transducer arrays

GUPTA LALIT

Method to improve unfolding in Petri nets

Method and apparatus for automated ultrasonic doppler angle and flow velocity estimation

MCGRAW HILL SCHOOL EDUCATION HOLDINGS LLC

Systems and methods for computationally distinguishing handwritten pencil marks from preprinted marks in a scanned document

ANAND AJAY

Automated doppler velocimetry using a low-cost transducer

RUBRIK INC

Techniques for upgrading and accessing metadata

ARM LIMTED

Transition coupling circuitry for memory applications