Inventor

GEETHA VEDARAMAN

US34 patents

⚠️ This page may combine multiple inventors who share the name “GEETHA VEDARAMAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GEETHA VEDARAMAN

INTEL CORP

High performance interconnect

High performance interconnect

Method and system for performing data movement operations with read snapshot and in place write update

Two level memory full line writes

Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory

High performance interconnect

High performance interconnect

Multiple dies hardware processors and methods

Method and system for performing data movement operations with read snapshot and in place write update

High performance interconnect

High performance interconnect

Multiple dies hardware processors and methods

Method and system for performing data movement operations with read snapshot and in place write update

Multiple dies hardware processors and methods

Multiple dies hardware processors and methods

Method, apparatus and system for handling cache misses in a processor

Two level memory full line writes

Method, apparatus and system for optimizing cache memory transaction handling in a processor

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory

Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

Hybrid directory and snoopy-based coherency to reduce directory update overhead in two-level memory

Selective memory mode authorization enforcement

Mission-critical computing architecture

Cache coherency apparatus and method minimizing memory writeback operations

Clock signal modulation for processors

QUALCOMM INC

Methods and systems for memory bandwidth control

Methods and systems for memory bandwidth control

Efficiently striping ordered PCIe writes across multiple socket-to-socket links

Methods and systems for memory bandwidth control

MOGA ADRIAN C

Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines

GEETHA VEDARAMAN

Value of forward state by increasing local caching agent forwarding

BAUM ALLEN J

Dynamically routing data responses directly to requesting processor core