Inventor

CHEEK JON D

US48 patents

⚠️ This page may combine multiple inventors who share the name “CHEEK JON D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEEK JON D

ADVANCED MICRO DEVICES INC

Method and apparatus for characterizing semiconductor device performance variations based on independent critical dimension measurements

Removable spacer technique

Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Formation and control of a vertically oriented transistor channel length

Trench transistor and isolation trench

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto

Method of forming silicide layers over a plurality of semiconductor devices

Method of making transistors with gate insulation layers of differing thickness

Parallel and series-coupled transistors having gate conductors formed on sidewall surfaces of a sacrificial structure

Angled halo implant tailoring using implant mask

Method for forming integrated circuit gate conductors from dual layers of polysilicon

Transistor formation with local interconnect overetch immunity

Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant

Transistor with integrated poly/metal gate electrode

Transistor formation with LI overetch immunity

Method of making high performance MOSFET with integrated poly/metal gate electrode

Stacked poly-oxide-poly gate for improved silicide formation

Asymmetrical P-channel transistor having a boron migration barrier and a selectively formed sidewall spacer

Method of forming trench transistor and isolation trench

Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto

Ultra short transistor channel length dictated by the width of a sidewall spacer

Gate conductor formed within a trench bounded by slanted sidewalls

Test structure for determining how lithographic patterning of a gate conductor affects transistor properties

Method for offsetting a silicide process from a gate electrode of a semiconductor device

Method of reducing STI divot formation during semiconductor device fabrication

Method of analyzing the effects of shadowing of angled halo implants

Semiconductor device and method of making semiconductor device comprising multiple stacked hybrid orientation layers

Transistor device having an enhanced width dimension and a method of making same

Test structure for measuring effective channel length of a transistor

Method of silicide formation by silicon pretreatment

Method for forming a retrograde impurity profile

Semiconductor topography including integrated circuit gate conductors incorporating dual layers of polysilicon

Asymmetrical transistor structure

Method of forming source/drain regions in a semiconductor device

Self-aligned VT implant

Method of controlling junction recesses in a semiconductor device

Test structure for determining the properties of densely packed transistors

Method for reducing junction capacitance using a halo implant photomask

Self-aligned Vt implant

Poly gate CD passivation for metrology control

Two level transistor formation for optimum silicon utilization

Method of fabricating a deep source/drain

Asymmetrical n-channel transistor having LDD implant only in the drain region

FREESCALE SEMICONDUCTOR INC

Interlayer dielectric under stress for an integrated circuit

Methodology to reduce SOI floating-body effect

Embedded NVM in a HKMG process

Embedded NVM in a HKMG process