Inventor
PETOLINO JOSEPH A
US7 patents
Patents
7 patentsUS5095424AMar 10, 1992
Computer system architecture implementing split instruction and operand cache line-pair-state management
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US4888689ADec 19, 1989
Apparatus and method for improving cache access throughput in pipelined processors
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US4855904AAug 8, 1989
Cache storage queue
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US4852100AJul 25, 1989
Error detection and correction scheme for main storage unit
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US4768197AAug 30, 1988
Cache error code update
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US4872111AOct 3, 1989
Monolithic semi-custom IC having standard LSI sections and coupling gate array sections
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US4722046AJan 26, 1988
Cache storage priority
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