Inventor

SAGER DAVID J

US71 patents

⚠️ This page may combine multiple inventors who share the name “SAGER DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAGER DAVID J

INTEL CORP

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Multi-threading for a processor utilizing a replay queue

Breaking replay dependency loops in a processor using a rescheduled replay queue

Data speculatable processor having reply architecture

Apparatus and method for address calculation

Processor with registers storing committed/speculative data and a RAT state history recovery mechanism with retire pointer

Trace based instruction caching

Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter

Storing of instructions relating to a stalled thread

Processor including replay queue to break livelocks

Way-predicting cache memory

Scheduling operations using a dependency matrix

Processor having execution core sections operating at different clock rates

Trace based instruction caching

Computer processor with a replay system

Computer processor with a replay system having a plurality of checkers

Method and apparatus for assigning thread priority in a processor or the like

Stopping replay tornadoes

Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor

Processor having execution core sections operating at different clock rates

Processor having execution core sections operating at different clock rates

Multi-threading techniques for a processor utilizing a replay queue

Processor with a replay system that includes a replay queue for improved throughput

Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection

Processor having replay architecture with fast and slow replay paths

Interface to a memory system for a processor having a replay system

Computer processor having a checker

Computer processor with instruction-specific schedulers

Fusing load and alu operations

DIGITAL EQUIPMENT CORP

Multi instruction register mapper

Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery

Instruction coding to support parallel execution of programs

Method and apparatus for parallel execution of computer programs using information providing for reconstruction of a logical sequential program

Next line prediction apparatus for a pipelined computed system

Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline

Past-history filtered branch prediction

Apparatus and method for speculatively executing instructions in a computer system

Past-history filtered branch prediction

Multiple block line prediction

Cache memory system

Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems

Memory reference tagging

Mechanism for enforcing the correct order of instruction execution

Method and apparatus for propagating exception conditions of a computer system

Method and apparatus for realignment of synchronous data

Method and apparatus for stabilized data transmission

Lockout registers

Method and apparatus for stabilized data transmission

(unassigned)

Hardware instruction scheduler for short execution unit latencies

HEWLETT PACKARD DEVELOPMENT CO

Mechanism for executing computer instructions in parallel