Inventor
BISSETT THOMAS D
US30 patents
⚠️ This page may combine multiple inventors who share the name “BISSETT THOMAS D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
DIGITAL EQUIPMENT CORP
17 patentsUS5588112ADec 24, 1996
DMA controller for memory scrubbing
DIGITAL EQUIPMENT CORP176 citations98
US5255367AOct 19, 1993
Fault tolerant, synchronized twin computer system with error checking of I/O communication
DIGITAL EQUIPMENT CORP127 citations96
US5249187ASep 28, 1993
Dual rail processors with error checking on I/O reads
DIGITAL EQUIPMENT CORP64 citations96
US5005174AApr 2, 1991
Dual zone, fault tolerant computer system with error checking in I/O writes
DIGITAL EQUIPMENT CORP70 citations96
US5347559ASep 13, 1994
Apparatus and method of data transfer between systems using different clocks
DIGITAL EQUIPMENT CORP78 citations95
US5339408AAug 16, 1994
Method and apparatus for reducing checking costs in fault tolerant processors
DIGITAL EQUIPMENT CORP56 citations95
US5291494AMar 1, 1994
Method of handling errors in software
DIGITAL EQUIPMENT CORP107 citations95
US5153881AOct 6, 1992
Method of handling errors in software
DIGITAL EQUIPMENT CORP74 citations95
US5065312ANov 12, 1991
Method of converting unique data to system data
DIGITAL EQUIPMENT CORP58 citations95
US4907228AMar 6, 1990
Dual-rail processor with error checking at single rail interfaces
DIGITAL EQUIPMENT CORP105 citations94
US4916704AApr 10, 1990
Interface of non-fault tolerant components to fault tolerant system
DIGITAL EQUIPMENT CORP56 citations93
US5099485AMar 24, 1992
Fault tolerant computer systems with fault isolation and repair
DIGITAL EQUIPMENT CORP100 citations92
US5068851ANov 26, 1991
Apparatus and method for documenting faults in computing modules
DIGITAL EQUIPMENT CORP65 citations92
US5068780ANov 26, 1991
Method and apparatus for controlling initiation of bootstrap loading of an operating system in a computer system having first and second discrete computing zones
DIGITAL EQUIPMENT CORP58 citations92
US5185877AFeb 9, 1993
Protocol for transfer of DMA data
DIGITAL EQUIPMENT CORP68 citations91
US5251227AOct 5, 1993
Targeted resets in a data processor including a trace memory to store transactions
DIGITAL EQUIPMENT CORP48 citations90
US5048022ASep 10, 1991
Memory device with transfer of ECC signals on time division multiplexed bidirectional lines
DIGITAL EQUIPMENT CORP45 citations87
MARATHON TECHN CORP
8 patentsUS6279119B1Aug 21, 2001
Fault resilient/fault tolerant computing
MARATHON TECHN CORP87 citations97
US5896523AApr 20, 1999
Loosely-coupled, synchronized execution
MARATHON TECHN CORP139 citations97
US5600784AFeb 4, 1997
Fault resilient/fault tolerant computing
MARATHON TECHN CORP106 citations97
US6473869B2Oct 29, 2002
Fault resilient/fault tolerant computing
MARATHON TECHN CORP70 citations95
US5790397AAug 4, 1998
Fault resilient/fault tolerant computing
MARATHON TECHN CORP78 citations94
US5615403AMar 25, 1997
Method for executing I/O request by I/O processor after receiving trapped memory address directed to I/O device from all processors concurrently executing same program
MARATHON TECHN CORP60 citations94
US6205565B1Mar 20, 2001
Fault resilient/fault tolerant computing
MARATHON TECHN CORP35 citations91
US7877552B2Jan 25, 2011
Symmetric multiprocessor fault tolerant computer system
MARATHON TECHN CORP5 citations60
STRATUS TECH BERMUDA LTD
3 patentsUS9588844B2Mar 7, 2017
Checkpointing systems and methods using data forwarding
STRATUS TECH BERMUDA LTD15 citations83
US9760442B2Sep 12, 2017
Method of delaying checkpoints by inspecting network packets
STRATUS TECH BERMUDA LTD13 citations81
US9652338B2May 16, 2017
Dynamic checkpointing systems and methods
STRATUS TECH BERMUDA LTD15 citations81