Inventor

HARATSCH ERICH FRANZ

US48 patents

⚠️ This page may combine multiple inventors who share the name “HARATSCH ERICH FRANZ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HARATSCH ERICH FRANZ

SEAGATE TECHNOLOGY LLC

Read disturb detection based on dynamic bit error rate estimation

Open block handling to reduce write errors

Adaptive read retry optimization

Reordered data deduplication in storage devices

Symbol pair encoding for data compression

Reordered local data deduplication in storage devices

Open block handling to reduce write errors

Controlling SSD performance by queue depth

Memory access operation suspend/resume

Block health checking

Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells

Mitigating data errors in a storage device

Storage area retirement in a storage device

Recovering from hard decoding errors by remapping log likelihood ratio values read from NAND memory cells

Adaptive read retry optimization

Mitigating data errors in a storage device

Controlling SSD performance by the number of active memory dies

Controlling SSD performance by the number of active memory dies

Code rate adaptation

Logical to physical data storage mapping

Storage area retirement in a storage device

Enhanced address compaction

AGERE SYSTEMS INC

Method and apparatus for iterative error-erasure decoding

Method and apparatus for reduced state sequence estimation with tap-selectable decision-feedback

Method and apparatus for reducing the computational complexity and relaxing the critical path of reduced state sequence estimation (RSSE) techniques

Method and apparatus for pipelined joint equalization and decoding for gigabit communications

Method and apparatus for reduced-state viterbi detection in a read channel of a magnetic recording system

Pipelined decision-feedback unit in a reduced-state viterbi detector with local feedback

Method and apparatus for precomputation and pipelined selection of intersymbol interference estimates in a reduced-state Viterbi detector

Method and apparatus for multiple step Viterbi detection with local feedback

Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced-state Viterbi detector

Method and apparatus for-soft-output viterbi detection using a multiple-step trellis

Method and apparatus for joint equalization and decoding of multilevel codes

Method and apparatus for pipelined joint equalization and decoding for gigabit communications

Method and apparatus for precomputation and pipelined selection of branch metrics in a reduced state Viterbi detector

Path metric difference computation unit for computing path differences through a multiple-step trellis

Method and apparatus for pipelined joint equalization and decoding for gigabit communications

Reliability unit for determining a reliability value for at least one bit decision

HARATSCH ERICH FRANZ

Method and apparatus for iterative error-erasure decoding

Storage media inter-track interference cancellation

AZADET KAMERAN

Method and apparatus for joint equalization and decoding of multidimensional codes transmitted over multiple symbol durations

Method and apparatus for joint equalization and decoding of multilevel codes

LUCENT TECHNOLOGIES INC

Method and apparatus for shortening the critical path of reduced complexity sequence estimation techniques

LUND TIMOTHY B

Storage media inter-track interference cancellation

ALCATEL LUCENT USA INC

Hybrid memory architecture for reduced state sequence estimation (RSSE) techniques

MATHEW GEORGE

Energy-based inter-track interference cancellation

ASHLEY JONATHAN JAMES

Methods and apparatus for processing a received signal using a multiple-step trellis and selection signals for multiple trellis paths

FITZPATRICK KELLY KNUDSON

Path comparison unit for determining paths in a trellis that compete with a survivor path