Inventor

WALKER ANDREW J

US82 patents

⚠️ This page may combine multiple inventors who share the name “WALKER ANDREW J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WALKER ANDREW J

MATRIX SEMICONDUCTOR INC

NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same

Method for fabricating programmable memory array structures incorporating series-connected transistor strings

Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication

Monolithic three dimensional array of charge storage devices containing a planarized surface

TFT mask ROM and method for making same

Inverted staggered thin film transistor with salicided source/drain structures and method of making same

Thin film transistors with vertically offset drain regions

Rail stack array of charge storage devices and method of making same

Two mask floating gate EEPROM and method of making

Thin film transistor with metal oxide layer and method of making same

Semiconductor device with localized charge storage dielectric and method of making same

High density 3D rail stack arrays

High density 3d rail stack arrays and method of making

Formation of thin channels for TFT devices to ensure low variability of threshold voltages

SANDISK 3D LLC

Method for forming doped polysilicon via connecting polysilicon layers

Doped polysilicon via connecting polysilicon layers

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Memory array incorporating memory cells arranged in NAND strings

Programmable memory array structure incorporating series-connected transistor strings and methods for fabrication and operation of same

Junction diode comprising varying semiconductor compositions

Dense arrays and charge storage devices

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

TFT mask ROM and method for making same

Two mask floating gate EEPROM and method of making

Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block

Semiconductor device with localized charge storage dielectric and method of making same

Method for forming doped polysilicon via connecting polysilicon layers

SPIN MEMORY INC

Three dimensional perpendicular magnetic junction with thin-film transistor

Integration of epitaxially grown channel selector with two terminal resistive switching memory element

Integration of epitaxially grown channel selector with MRAM device

Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels

Method of making a three dimensional perpendicular magnetic tunnel junction with thin-film transistor

Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels

Annular vertical Si etched channel MOS devices

Fabrication methods of forming annular vertical SI etched channel MOS devices

Fabrication of a perpendicular magnetic tunnel junction (PMTJ) using block copolymers

SCHILTRON CORP

Nonvolatile memory with backplate

Dual-gate device

Dual-gate nonvolatile memory and method of program inhibition

Independent vertical-gate 3-D NAND memory circuit

WALKER ANDREW J

Dual-gate device and method

Voltage protection device

ESD protection device with charge collections regions

CYPRESS SEMICONDUCTOR CORP

Silicon controlled rectifier electrostatic discharge clamp for a high voltage laterally diffused MOS transistor

Circuits providing ESD protection to high voltage laterally diffused metal oxide semiconductor (LDMOS) transistors

SANDISK CORP

TFT mask ROM and method for making same

MATRIX SEMICONDUCTORS INC

Storage layer optimization of a nonvolatile memory device

PHILIPS CORP

Semiconductor device having a nonvolatile memory cell in which the floating gate is charged with hot charge carriers at the source side

INTEGRATED SILICON SOLUTION CAYMAN INC

Three dimensional perpendicular magnetic tunnel junction with thin film transistor array

SPIN TRANSFER TECH INC

Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)