Inventor

FASOLI LUCA G

US49 patents

⚠️ This page may combine multiple inventors who share the name “FASOLI LUCA G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FASOLI LUCA G

SANDISK 3D LLC

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Memory array incorporating memory cells arranged in NAND strings

Integrated circuit including memory array incorporating multiple types of NAND string structures

Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders

Method and apparatus for incorporating block redundancy in a memory array

NAND memory array incorporating capacitance boosting of channel regions in unselected memory cells and method for operation of same

Apparatus and method for hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

Apparatus and method for memory operations using address-dependent conditions

Passive element memory array incorporating reversible polarity word line and bit line decoders

Method for using dual data-dependent busses for coupling read/write circuits to a memory array

Dual data-dependent busses for coupling read/write circuits to a memory array

Method for controlling current during programming of memory cells

Memory device for protecting memory cells during programming

System architecture and method for three-dimensional memory

Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers

Decoding circuit for non-binary groups of memory line drivers

Hierarchical decoding of dense memory arrays using multiple levels of multiple-headed decoders

Memory array incorporating mirrored NAND strings and non-shared global bit lines within a block

Dual-mode decoder circuit, integrated circuit memory array incorporating same, and related methods of operation

Level shifter circuit incorporating transistor snap-back protection

Memory device for protecting memory cells during programming

Method for using two data busses for memory array block selection

Apparatus for reading a multi-level passive element memory cell array

Method for reading a multi-level passive element memory cell array

Reversible polarity decoder circuit

Memory array incorporating two data busses for memory array block selection

Reversible-polarity decoder circuit and method

Method for incorporating transistor snap-back protection in a level shifter circuit

Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers

Hierarchical bit line bias bus for block selectable memory array

Method for using a hierarchical bit line bias bus for block selectable memory array

Method for protecting memory cells during programming

Method for using a reversible polarity decoder circuit

Method for using a spatially distributed amplifier circuit

Spatially distributed amplifier circuit

SCHEUERLEIN ROY E

Capacitive discharge method for writing to non-volatile memory

Three-dimensional memory device incorporating segmented array line memory array

Memory array circuit incorporating multiple array block selection and related method

Three-dimensional memory device incorporating segmented array line memory array

Capacitive discharge method for writing to non-volatile memory

Decoder circuitry providing forward and reverse modes of memory array operation and method for biasing same

MATRIX SEMICONDUCTOR INC

NAND memory array incorporating multiple write pulse programming of individual memory cells and method for operation of same

Multibank memory on a die

System and method of controlling a three-dimensional memory

FASOLI LUCA G

Non-volatile memory array architecture incorporating 1T-1R near 4F2 memory cell

Smart detection circuit for writing to non-volatile storage

SAN DISK 3D LLC

Memory device for controlling current during programming of memory cells

YAN TIANHONG

Three dimensional memory system with page of data across word lines

ST MICROELECTRONICS INC

Programmable system device having a shared power supply voltage generator for FLASH and PLD modules