Inventor

HATHAWAY DAVID J

US114 patents

⚠️ This page may combine multiple inventors who share the name “HATHAWAY DAVID J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HATHAWAY DAVID J

IBM

Method for making integrated circuits having gated clock trees

Use of redundant routes to increase the yield and reliability of a VLSI layout

System and method for correlated process pessimism removal for static timing analysis

Method and system for evaluating timing in an integrated circuit

Method for handling coupling effects in static timing analysis

Incremental timing analysis

Method for tuning a digital design for synthesized random logic circuit macros in a continuous design space with optional insertion of multiple threshold voltage devices

Concurrent logical and physical construction of voltage islands for mixed supply voltage designs

Incremental design tuning and decision mediator

Latch clustering for power optimization

Method and system for evaluating timing in an integrated circuit

Method of integrated circuit design checking using progressive individual network analysis

System and method for inserting leakage reduction control in logic circuits

Timing analysis method for PLLS

Delay model abstraction

Logic path length reduction using boolean minimization

Clock aware placement

Slack sensitivity to parameter variation based timing analysis

Voltage dependent parameter analysis

Method for reducing switching activity during a scan operation with limited impact on the test coverage of an integrated circuit

Distributed static timing analysis

Distributed static timing analysis

Method and apparatus for optimizing a logic network

Clock tree distribution generation by determining allowed placement regions for clocked elements

Parameter variation tolerant method for circuit design optimization

Generation of refined switching windows in static timing analysis

Method and apparatus for reducing power consumption in VLSI circuit designs

Method of optimizing and analyzing selected portions of a digital integrated circuit

Network timing analysis method which eliminates timing variations between signals traversing a common circuit path

Method and apparatus for making a skew-controlled signal distribution network

Optimizing placement of circuit resources using a globally accessible placement memory

Optimizing placement of circuit resources using a globally accessible placement memory

System and method for maintaining slack continuity in incremental statistical timing analysis

Modeling multi-patterning variability with statistical timing

Systems and methods for correlated parameters in statistical static timing analysis

Hierarchical design of integrated circuits with multi-patterning requirements

Reducing runtime and memory requirements of static timing analysis

Systems and methods for correlated parameters in statistical static timing analysis

Parasitic extraction in an integrated circuit with multi-patterning requirements

Method for performing a parallel static timing analysis using thread-specific sub-graphs

Representing and propagating a variational voltage waveform in statistical static timing analysis of digital circuits

Slack sensitivity to parameter variation based timing analysis

Method of generating wiring routes with matching delay in the presence of process variation

Method for fast incremental calculation of an impact of coupled noise on timing

Method of identifying paths with delays dominated by a particular factor

System and method of analyzing timing effects of spatial distribution in circuits

Method of achieving timing closure in digital integrated circuits by optimizing individual macros

FOREMAN ERIC A

Systems and methods for correlated parameters in statistical static timing analysis

System and method for common history pessimism relief during static timing analysis

GLOBALFOUNDRIES INC

Dynamic and adaptive timing sensitivity during static timing analysis using look-up table