Inventor
POLSON ANTHONY D
US27 patents
⚠️ This page may combine multiple inventors who share the name “POLSON ANTHONY D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
25 patentsUS7089143B2Aug 8, 2006
Method and system for evaluating timing in an integrated circuit
IBM41 citations96
US7444608B2Oct 28, 2008
Method and system for evaluating timing in an integrated circuit
IBM13 citations93
US7401307B2Jul 15, 2008
Slack sensitivity to parameter variation based timing analysis
IBM24 citations92
US7716616B2May 11, 2010
Slack sensitivity to parameter variation based timing analysis
IBM12 citations84
US7489204B2Feb 10, 2009
Method and structure for chip-level testing of wire delay independent of silicon delay
IBM17 citations84
US7418689B2Aug 26, 2008
Method of generating wiring routes with matching delay in the presence of process variation
IBM12 citations84
US7280939B2Oct 9, 2007
System and method of analyzing timing effects of spatial distribution in circuits
IBM13 citations84
US7890906B2Feb 15, 2011
Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells
IBM8 citations83
US7840864B2Nov 23, 2010
Functional frequency testing of integrated circuits
IBM8 citations83
US7810054B2Oct 5, 2010
Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point
IBM11 citations82
US7877714B2Jan 25, 2011
System and method to optimize semiconductor power by integration of physical design timing and product performance measurements
IBM10 citations81
US7487487B1Feb 3, 2009
Design structure for monitoring cross chip delay variation on a semiconductor device
IBM8 citations79
US7865861B2Jan 4, 2011
Method of generating wiring routes with matching delay in the presence of process variation
IBM5 citations74
US7870525B2Jan 11, 2011
Slack sensitivity to parameter variation based timing analysis
IBM5 citations73
US7849433B2Dec 7, 2010
Integrated circuit with uniform polysilicon perimeter density, method and design structure
IBM7 citations73
US7840863B2Nov 23, 2010
Functional frequency testing of integrated circuits
IBM4 citations72
US7290191B2Oct 30, 2007
Functional frequency testing of integrated circuits
IBM6 citations72
US9310426B2Apr 12, 2016
On-going reliability monitoring of integrated circuit chips in the field
IBM6 citations71
US7302673B2Nov 27, 2007
Method and system for performing shapes correction of a multi-cell reticle photomask design
IBM7 citations71
US7962874B2Jun 14, 2011
Method and system for evaluating timing in an integrated circuit
IBM4 citations63
US7823115B2Oct 26, 2010
Method of generating wiring routes with matching delay in the presence of process variation
IBM4 citations63
US7805693B2Sep 28, 2010
IC chip design modeling using perimeter density to electrical characteristic correlation
IBM2 citations62
US7765351B2Jul 27, 2010
High bandwidth low-latency semaphore mapped protocol (SMP) for multi-core systems on chips
IBM6 citations62
US7521973B1Apr 21, 2009
Clock-skew tuning apparatus and method
IBM4 citations56
US7680626B2Mar 16, 2010
System and method of analyzing timing effects of spatial distribution in circuits
IBM0 citations52