P

Inventor

GLUSCHENKOV OLEG G

US28 patents
⚠️ This page may combine multiple inventors who share the name “GLUSCHENKOV OLEG G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

24 patents
US7247534B2Jul 24, 2007

Silicon device on Si:C-OI and SGOI and method of manufacture

IBM95 citations99
US7198995B2Apr 3, 2007

Strained finFETs and method of manufacture

IBM154 citations99
US7015082B2Mar 21, 2006

High mobility CMOS circuits

IBM159 citations99
US6891192B2May 10, 2005

Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regions

IBM179 citations99
US7279413B2Oct 9, 2007

High-temperature stable gate structure with metallic electrode

IBM53 citations96
US7223994B2May 29, 2007

Strained Si on multiple materials for bulk or SOI substrates

IBM21 citations93
US7291528B2Nov 6, 2007

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

IBM16 citations92
US7144767B2Dec 5, 2006

NFETs using gate induced stress modulation

IBM24 citations92
US6989322B2Jan 24, 2006

Method of forming ultra-thin silicidation-stop extensions in mosfet devices

IBM27 citations92
US7683418B2Mar 23, 2010

High-temperature stable gate structure with metallic electrode

IBM10 citations84
US7396714B2Jul 8, 2008

Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regions

IBM11 citations84
US7170126B2Jan 30, 2007

Structure of vertical strained silicon devices

IBM16 citations84
US6974991B2Dec 13, 2005

DRAM cell with buried collar and self-aligned buried strap

IBM12 citations81
US7402870B2Jul 22, 2008

Ultra shallow junction formation by epitaxial interface limited diffusion

IBM5 citations74
US7119403B2Oct 10, 2006

High performance strained CMOS devices

IBM7 citations74
US7521345B2Apr 21, 2009

High-temperature stable gate structure with metallic electrode

IBM5 citations73
US7847358B2Dec 7, 2010

High performance strained CMOS devices

IBM3 citations63
US7560328B2Jul 14, 2009

Strained Si on multiple materials for bulk or SOI substrates

IBM4 citations63
US7285826B2Oct 23, 2007

High mobility CMOS circuits

IBM4 citations63
US7205207B2Apr 17, 2007

High performance strained CMOS devices

IBM2 citations63
US8013392B2Sep 6, 2011

High mobility CMOS circuits

IBM1 citations52
US7816237B2Oct 19, 2010

Ultra shallow junction formation by epitaxial interface limited diffusion

IBM0 citations52
US7569848B2Aug 4, 2009

Mobility enhanced CMOS devices

IBM1 citations52
US7232774B2Jun 19, 2007

Polycrystalline silicon layer with nano-grain structure and method of manufacture

IBM0 citations50

CHIDAMBARRAO DURESETI

2 patents

CHEN HUAJIE

1 patent

CHIDAMBARRAO DURESTI

1 patent