Inventor

LEE CHONG H

US73 patents

⚠️ This page may combine multiple inventors who share the name “LEE CHONG H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE CHONG H

ALTERA CORP

Programmable logic devices with multi-standard byte synchronization and channel alignment for communication

Byte alignment for serial data receiver

Programmable logic device with high speed serial interface circuitry

Dynamically-adjustable differential output drivers

Byte alignment circuitry

Multi-standard clock rate matching circuitry

Multi-channel synchronization for programmable logic device serial interface

Clock signal circuitry for multi-protocol high-speed serial interface circuitry

Multiple transmit data rates in programmable logic device serial interface

Data converter with reduced component count for padded-protocol interface

Multiple data rates in programmable logic device serial interface

Programmable logic device serial interface having dual-use phase-locked loop circuitry

Method and system for operating a communication circuit configurable to support one or more data rates

Multi-protocol low latency automatic speed negotiation architecture for an embedded high speed serial interface in a programmable logic device

Dynamically-adjustable differential output drivers

Digital phase locked loop circuitry and methods

Byte alignment for serial data receiver

Programmable logic device with high speed serial interface circuitry

Programmable logic device with high speed serial interface circuitry

Voltage controlled oscillator programmable delay cells

Field programmable gate array architectures and methods for supporting forward error correction

Integrated hard-wired or partly hard-wired CRC generation and/or checking architecture for a physical coding sublayer in a programmable logic device

Programmable bit error rate monitor for serial interface

Circuitry for providing configurable running disparity enforcement in 8B/10B encoding and error detection

Correlating high-speed serial interface data and FIFO status signals in programmable logic devices

CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device

DPRIO for embedded hard IP

Digital phase locked loop circuitry and methods

Dynamically-adjustable differential output drivers

Next generation 8B10B architecture

Next generation 8B10B architecture

Data converter with multiple conversions for padded-protocol interface

Byte alignment circuitry

Programmable logic devices with multi-standard byte synchronization and channel alignment for communication

Configurable multi-lane scrambler for flexible protocol support

Heterogeneous transceiver architecture for wide range programmability of programmable logic devices

Programmable logic device with high speed serial interface circuitry

Megafunction block and interface

Oversampling with programmable pointer adjustment

VIJAYARAGHAVAN DIVYA

Method and system for operating a communication circuit during a low-power state

Method and system for transitioning a communication circuit to a low-power state

Method and system for efficiently transitioning a communication circuit from a low-power state

Multi-protocol configurable transceiver with independent channel-based PCS in an integrated circuit

Multi-protocol channel-aggregated configurable transceiver in an integrated circuit

Configurable multi-standard device interface

Multi-protocol multiple-data-rate auto-speed negotiation architecture for a device

WORTMAN CURT

Configurable multi-lane scrambler for flexible protocol support

Flexible interface for stacked protocol in a programmable integrated circuit device

LEE CHONG H

Carrying case for a computer

SUH WON AMERICA INC

Dual purpose pallet sheet