Inventor
YUAN JINYONG
US35 patents
⚠️ This page may combine multiple inventors who share the name “YUAN JINYONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
ALTERA CORP
28 patentsUS7705628B1Apr 27, 2010
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
ALTERA CORP13 citations93
US9053274B1Jun 9, 2015
Register retiming technique
ALTERA CORP14 citations92
US7558812B1Jul 7, 2009
Structures for LUT-based arithmetic in PLDs
ALTERA CORP25 citations92
US7424689B1Sep 9, 2008
Gated clock conversion
ALTERA CORP16 citations92
US8806399B1Aug 12, 2014
Register retiming technique
ALTERA CORP4 citations84
US7406668B1Jul 29, 2008
Methods for producing mappings of logic suitable for FPGA and structured ASIC implementations
ALTERA CORP11 citations84
US7373631B1May 13, 2008
Methods of producing application-specific integrated circuit equivalents of programmable logic
ALTERA CORP12 citations84
US7360197B1Apr 15, 2008
Methods for producing equivalent logic designs for FPGAs and structured ASIC devices
ALTERA CORP9 citations84
US7246340B1Jul 17, 2007
Timing-driven synthesis with area trade-off
ALTERA CORP16 citations84
US7330052B2Feb 12, 2008
Area efficient fractureable logic elements
ALTERA CORP13 citations83
US7246339B2Jul 17, 2007
Methods for creating and expanding libraries of structured ASIC logic and other functions
ALTERA CORP11 citations83
US7386828B1Jun 10, 2008
SAT-based technology mapping framework
ALTERA CORP13 citations81
US7631284B1Dec 8, 2009
Graphical user aid for technology migration and associated methods
ALTERA CORP8 citations79
US7308671B1Dec 11, 2007
Method and apparatus for performing mapping onto field programmable gate arrays utilizing fracturable logic cells
ALTERA CORP8 citations74
US7249329B1Jul 24, 2007
Technology mapping techniques for incomplete lookup tables
ALTERA CORP7 citations74
US9658830B1May 23, 2017
Structures for LUT-based arithmetic in PLDs
ALTERA CORP2 citations73
US7386819B1Jun 10, 2008
Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
ALTERA CORP6 citations73
US7890910B1Feb 15, 2011
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
ALTERA CORP5 citations72
US7587688B1Sep 8, 2009
User-directed timing-driven synthesis
ALTERA CORP4 citations63
US7397726B1Jul 8, 2008
Flexible RAM clock enable
ALTERA CORP3 citations63
US7373630B1May 13, 2008
Methods for improved structured ASIC design
ALTERA CORP4 citations63
US7992110B1Aug 2, 2011
Methods of verifying functional equivalence between FPGA and structured ASIC logic cells
ALTERA CORP4 citations62
US7725871B1May 25, 2010
SAT-based technology mapping framework
ALTERA CORP3 citations60
US7126858B1Oct 24, 2006
Apparatus for emulating asynchronous clear in memory structure and method for implementing the same
ALTERA CORP2 citations59
US7363596B1Apr 22, 2008
Methods for storing and naming static library cells for lookup by logic synthesis and the like
ALTERA CORP4 citations58
US8006206B1Aug 23, 2011
Gated clock conversion
ALTERA CORP1 citations52
US7415693B1Aug 19, 2008
Method and apparatus for reducing synthesis runtime
ALTERA CORP1 citations52
US9172378B1Oct 27, 2015
Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers
ALTERA CORP0 citations51