Inventor

BAECKLER GREGG WILLIAM

US71 patents

⚠️ This page may combine multiple inventors who share the name “BAECKLER GREGG WILLIAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAECKLER GREGG WILLIAM

ALTERA CORP

Apparatus and methods for tuning a communication link for power conservation

First-in first-out circuits and methods

Heterogeneous labs

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

Hardware acceleration of functional factoring

Register retiming technique

Method and apparatus for deriving signal activities for power analysis and optimization

Register retiming technique

State machine recognition and optimization

Methods of producing application-specific integrated circuit equivalents of programmable logic

SAT-based technology mapping framework

Technology mapping techniques for incomplete lookup tables

Methods and apparatus for performing bit swapping in clock data recovery circuitry

High-speed data communications architecture

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers

Preemptively generating statistical feedback on a design file and presenting the feedback in an input context

Central alignment circutry for high-speed serial receiver circuits

Hierarchical cyclic redundancy check circuitry

Methods and apparatus for detecting and correcting errors in high-speed serial communications systems

Method and apparatus for performing parallel synthesis on a field programmable gate array

Hardware acceleration of functional factoring

Method for early logic mapping during FPGA synthesis

Fast method for functional mapping to incomplete LUT pairs

SAT-based technology mapping framework

INTEL CORP

High performance regularized network-on-chip architecture

Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extension

Programmable logic device with fine-grained disaggregation

Geometric synthesis

Circuitry for low-precision deep learning

Hazard mitigation for lightweight processor cores

Programmable integrated circuit underlay

Deterministic clustering and packing method for random logic on programmable integrated circuits

Method and apparatus for performing field programmable gate array packing with continuous carry chains

Programmable-logic-directed multiplier mapping

Programmable logic device with fine-grained disaggregation

Programmable logic device with fine-grained disaggregation

Method and apparatus for performing synthesis for field programmable gate array embedded feature placement

Programmable logic device with fine-grained disaggregation

Reduction operation mapping systems and methods

High performance regularized network-on-chip architecture

Machine learning training architecture for programmable devices

Vector processor architectures

Method and apparatus for performing multiplier regularization

BAECKLER GREGG WILLIAM

Method and apparatus for performing parallel synthesis on a field programmable gate array

Method and apparatus for extracted synthesis gate characteristics model

Network interface circuitry with flexible memory addressing capabilities

Signature based duplicate extraction

MENDEL DAVID W

Distributed burst error protection

VAN ANTWERPEN BABETTE

Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement

HUTTON MICHAEL D

Programmable logic device having logic elements with dedicated hardware to configure look up tables as registers