Inventor

CYPHER ROBERT E

US91 patents

⚠️ This page may combine multiple inventors who share the name “CYPHER ROBERT E”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CYPHER ROBERT E

SUN MICROSYSTEMS INC

Error detection/correction code which detects and corrects a first failing component and optionally a second failing component

Memory/Transmission medium failure handling controller and method

Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure

Computer system employing redundant cooling fans

Cache memory system including a partially hashed index

System and method for tolerating communication lane failures

Mechanism and method for cache snoop filtering

System and method for dynamic memory interleaving and de-interleaving

Method for in-place memory interleaving and de-interleaving

Multiprocessing system employing address switches to control mixed broadcast snooping and directory based coherency protocols transparent to active devices

ECC for component failures using Galois fields

Mechanism and method employing a plurality of hash functions for cache snoop filtering

System with a directory based coherency protocol and split ownership and access right coherence mechanism

Computer system employing redundant power distribution

Method and apparatus for implementing virtual transactional memory using cache line marking

Circuit board orientation in a computer system

Address packets with variable-size mask format

Efficient store queue architecture

Efficient marking of shared cache lines

Multi-node system with split ownership and access right coherence mechanism

Conditional synchronization mechanisms allowing multiple store operations to become visible while a flagged memory location is owned and remains unchanged

Apparatus and method for determining stack distance of running software for estimating cache miss rates based upon contents of a hash table

System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism

Data corruption avoidance in DRAM chip sparing

Computer system including a network employing redundant information and slicing

Cache coherence protocol with speculative writestream

Computer system implementing synchronized broadcast using timestamps

Centerplaneless computer system

Mechanism for maintaining cache consistency in computer systems

ORACLE AMERICA INC

Method and apparatus for tracking load-marks and store-marks on cache lines

Method and apparatus for supporting very large transactions

Starvation-avoiding unbounded transactional memory

Associating data source information with runtime events

System and method for efficient verification of memory consistency model compliance

Preventing store starvation in a system that supports marked coherence

Cache line marking with shared timestamps

CYPHER ROBERT E

Hierarchical bloom filters for facilitating concurrency control

Hard component failure detection and correction

Facilitating efficient transactional memory and atomic operations via cache line marking

Facilitating error detection and correction after a memory component failure

Bloom bounders for improved computer system performance

Mechanism for increasing parallelization in computer programs with read-after-write dependencies associated with prefix operations

Cache-coherency protocol with held state

IBM

Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations

Method of packet routing in torus networks with two buffers per edge

Method and apparatus for tolerating faults in mesh architectures

Method for generating hierarchical fault-tolerant mesh architectures

Method and apparatus for a fault-tolerant mesh with spare nodes

MOIR MARK S

System and method for executing a transaction using parallel co-transactions

DAGA BHARAT K

Memory system that supports probalistic component-failure correction with partial-component sparing