Inventor

SANKARAN JAGADEESH

US40 patents

⚠️ This page may combine multiple inventors who share the name “SANKARAN JAGADEESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SANKARAN JAGADEESH

TEXAS INSTRUMENTS INC

Method of context based adaptive binary arithmetic decoding with two part symbol decoding

Method of CABAC coefficient magnitude and sign decoding suitable for use on VLIW data processors

Method of CABAC significance MAP decoding suitable for use on VLIW data processors

Loop deblock filtering of block coded video in a very long instruction word processor

Displaying cache information using mark-up techniques

Register move instruction for section select of source operand

Method of context based adaptive binary arithmetic encoding with decoupled range re-normalization and bit insertion

Video coding with CABAC

Error correction structures and methods

Speculative load of look up table entries based upon coarse index calculation in parallel with fine index calculation

Error correction structures and methods

Cache inspection with inspection bypass feature

Providing information associated with a cache

Cache friendly method for performing inverse discrete wavelet transform

Vector table load instruction with address generation field to access table offset value

Mechanism for pipelining loops with irregular loop control

Vector processor calculation of local binary patterns

Speculative data loading using circular addressing or simulated circular addressing

NVIDIA CORP

Built-in self-test for a programmable vision accelerator of a system on a chip

Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip

Performing multiple point table lookups in a single cycle in a system on chip

Hardware accelerated anomaly detection using a min/max collector in a system on a chip

Using a hardware sequencer in a direct memory access system of a system on a chip

Programmable vision accelerator

Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip

Using a hardware sequencer in a direct memory access system of a system on a chip

Using per memory bank load caches for reducing power use in a system on a chip

Built-in self-test for a programmable vision accelerator of a system on a chip

Hardware accelerated anomaly detection using a min/max collector in a system on a chip

Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip

Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip

Using per memory bank load caches for reducing power use in a system on a chip

Performing load and permute with a single instruction in a system on a chip

Performing load and store operations of 2D arrays in a single cycle in a system on a chip

Reduced memory write requirements in a system on a chip using automatic store predication

Object detection using image alignment for autonomous machine applications

SANKARAN JAGADEESH

On-demand predicate registers

Methods and systems for direct memory access (DMA) in-flight status

HUNG CHING YU

Processor with table lookup processing unit

HUNG CHING-YU

Processor with instruction variable data distribution