Inventor

CHANDRA VIKAS

US56 patents

⚠️ This page may combine multiple inventors who share the name “CHANDRA VIKAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANDRA VIKAS

ADVANCED RISC MACH LTD

One-time and multi-time programming using a correlated electron switch

Circuit and method for configurable impedance array

CES-based latching circuits

Address dependent data encryption

Memory device and method of controlling a write operation within a memory device

Process variation compensation with correlated electron switch devices

Correlated electron switch device

Error detection circuitry for use with memory

Electrical component with random electrical characteristic

Spiking neural network

Correlated electron switch programmable fabric

Error detection in stored data values

Sequential storage circuitry for an integrated circuit

CES-based latching circuits

Logic encryption using on-chip memory cells

Method, system and device for correlated electron switch (CES) device operation

Storage circuit with random number generation mode

Circuit and method for configurable impedance array

Correlated electron switch programmable fabric

Computer implemented system and method for reducing failure in time soft errors of a circuit design

Circuit and method for configurable impedance array

Error detection in stored data values

Method and apparatus for memory wear leveling

CHANDRA VIKAS

Method of altering distribution of a chosen characteristic of a plurality of memory cells forming a memory device

Low overhead circuit and method for predicting timing errors

Apparatus and method for generating a random number

Single event upset error detection within sequential storage circuitry of an integrated circuit

Correction of single event upset error within sequential storage circuitry of an integrated circuit

Boosting voltage levels applied to an access control line when accessing storage cells in a memory

Memory with improved read stability

Hierarchical functional and variable composition diagramming of a programming class

IBM

Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus

Exception prediction before an actual exception during debugging

Exception prediction before an actual exception during debugging

Exception prediction before an actual exception during debugging

Multi-thread sequencing

Reliability index in software testing

NETIQ CORP

Methods, systems and computer program products for scheduled network performance testing

Methods, systems and computer program products for monitoring interrelated tasks executing on a computer using queues

Methods, systems and computer program products for coordination of operations for interrelated tasks

META PLATFORMS INC

Flexible compute array utilization in a tensor processor

Spatial tiling of compute arrays with shared control

Video reconstruction from videos with ultra-low frame-per-second

TABULA INC

Configurable IC with interconnect circuits that also perform storage operations

Configurable IC with interconnect circuits that also perform storage operations

META PLATFORMS TECH LLC

Systems and methods for distributing a neural network across multiple computing devices

Fusion and super-resolution of monochrome and color images using deep neural networks

Savi Direct LLC

Multipurpose bag

CHOUDHURY MIHIR RAJANIKANT

Storage circuitry and method with increased resilience to single event upsets

FACEBOOK TECH LLC

System and method for supporting alternate number format for efficient multiplication