Inventor

CHANG GWAN SIN

TW49 patents

⚠️ This page may combine multiple inventors who share the name “CHANG GWAN SIN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG GWAN SIN

TAIWAN SEMICONDUCTOR MFG CO LTD

FinFET device and method for fabricating same

Buried SiGe oxide FinFET scheme for device enhancement

Inducing localized strain in vertical nanowire transistors

Semiconductor device and manufacturing method thereof

System and method for performing extreme ultraviolet photolithography processes

System and method for performing extreme ultraviolet photolithography processes

Semiconductor structure and fabrication method thereof

FinFET device including an dielectric region and method for fabricating same

Tuning strain in semiconductor devices

System and method for performing extreme ultraviolet photolithography processes

Protection of MRAM from external magnetic field using magnetic-field-shielding structure

Method for manufacturing semiconductor device

Semiconductor device and manufacturing method thereof

Semiconductor structure and fabrication method thereof

Semiconductor device and manufacturing method thereof

Apparatus and method for prevention of contamination on collector of extreme ultraviolet light source

Nanowire stack GAA device and methods for producing the same

Method for fabricating FinFET including forming an oxide layer

Tuning strain in semiconductor devices

Method for inducing strain in vertical semiconductor columns

Thermally tuning strain in semiconductor devices

Semiconductor device and manufacturing method thereof

Methods for double-patterning-compliant standard cell design

Method for forming semiconductor structure with epitaxial growth structure

TAIWAN SEMICONDUCTOR MFG

Semiconductor device and fabricating the same

Source/drain stack stressor for semiconductor device

Method of merging color sets of layout

FinFET device and method of fabricating same

Tuning strain in semiconductor devices

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

Place-and-route layout method with same footprint cells

Method for inducing strain in vertical semiconductor columns

Thermally tuning strain in semiconductor devices

Semiconductor device and fabricating the same

System, method, and computer program product for matching cell layout of an integrated circuit design

Method for smart dummy insertion to reduce run time and dummy count

Method for optimally converting a circuit design into a semiconductor device

System, method, and computer program product for matching cell layout of an integrated circuit design

CHEN HUANG-YU

Routing system and method for double patterning technology

Methods for double-patterning-compliant standard cell design

SU KE-YING

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

Accurate parasitic capacitance extraction for ultra large scale integrated circuits

LU LEE-CHUNG

Performance-aware logic operations for generating masks

Performance-aware logic operations for generating masks

CHEN PI-TSUNG

Decomposing integrated circuit layout

CHUANG HARRY

3-dimensional device design layout

CHENG YI-KAN

System and method for design-for-manufacturability data encryption

CHANG GWAN SIN

IC design flow enhancement with CMP simulation

HOU CLIFF

Method of generating technology file for integrated circuit design tools