Inventor

WEI ANDY

DE129 patents

⚠️ This page may combine multiple inventors who share the name “WEI ANDY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WEI ANDY

GLOBALFOUNDRIES INC

Forming a diffusion break during a RMG process

2D self-aligned via first process flow

Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same

Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints

Method of forming CMOS device having gate insulation layers of different type and thickness

CMOS device comprising MOS transistors with recessed drain and source areas and a SI/GE material in the drain and source areas of the PMOS transistor

Cut first alternative for 2D self-aligned via

Integrated circuits with nanowires and methods of manufacturing the same

Integrated circuits with relaxed silicon / germanium fins

Three-dimensional electrostatic discharge semiconductor device

Semiconductor devices with replacement gate structures having conductive contacts positioned therebetween

Methods of forming semiconductor devices with replacement gate structures

Enhanced confinement of high-K metal gate electrode structures by reducing material erosion of a dielectric cap layer upon forming a strain-inducing semiconductor alloy

Devices and methods of forming fins at tight fin pitches

Devices and methods of forming higher tunability FinFET varactor

Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings

Methods for fabricating integrated circuits

Replacement low-K spacer

ADVANCED MICRO DEVICES INC

Advanced technique for forming a transistor having raised drain and source regions

Different embedded strain layers in PMOS and NMOS transistors and a method of forming the same

Embedded strain layer in thin SOI transistors and a method of forming the same

Technique for forming a contact insulation layer with enhanced stress transfer efficiency

Technique for providing multiple stress sources in NMOS and PMOS transistors

Technique for forming recessed strained drain/source regions in NMOS and PMOS transistors

Gate structure and a transistor having asymmetric spacer elements and methods of forming the same

Shallow PN junction formed by in situ doping during selective growth of an embedded semiconductor alloy by a cyclic growth/etch deposition process

SOI device having a substrate diode with process tolerant configuration and method of forming the SOI device

Stress transfer in an interlayer dielectric by providing a stressed dielectric layer above a stress-neutral dielectric material in a semiconductor device

SOI transistor having an embedded strain layer and a reduced floating body effect and a method for forming the same

Transistor having a channel with tensile strain and oriented along a crystallographic orientation with increased charge carrier mobility

Technique for providing stress sources in transistors in close proximity to a channel region by recessing drain and source regions

Technique for forming a strained transistor by a late amorphization and disposable spacers

SOI transistor having a reduced body potential and a method of forming the same

Method for forming embedded strained drain/source regions based on a combined spacer and cavity etch process

WEI ANDY

Semiconductor device comprising metal gates and a silicon containing resistor formed on an isolation structure

Method for forming double gate and tri-gate transistors on a bulk substrate

Self-aligned multiple gate transistor formed on a bulk substrate

Fin-transistor formed on a patterned STI region by late fin etch

Method of forming a semiconductor device by using sacrificial gate electrodes and sacrificial self-aligned contact structures

Contact trenches for enhancing stress transfer in closely spaced transistors

SCHEIPER THILO

Self-aligned fin transistor formed on a bulk substrate by late fin etch

Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement

Short channel transistor with reduced length variation by using amorphous electrode material during implantation

MOWRY ANTHONY

Test structure for monitoring process characteristics for forming embedded semiconductor alloys in drain/source regions

In situ formed drain and source regions in a silicon/germanium containing transistor device

KRONHOLZ STEPHAN

Transistor with embedded Si/Ge material having reduced offset to the channel region

BAARS PETER

Method of forming self-aligned contacts for a semiconductor device

WIRBELEIT FRANK

Transistor with embedded strain-inducing material formed in diamond-shaped cavities based on a pre-amorphization

MULFINGER ROBERT

Transistor with embedded SI/GE material having enhanced across-substrate uniformity