Inventor

LEVITSKY OLEG

US21 patents

⚠️ This page may combine multiple inventors who share the name “LEVITSKY OLEG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEVITSKY OLEG

CADENCE DESIGN SYSTEMS INC

Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designs

Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs

System and method of generating hierarchical block-level timing constraints from chip-level timing constraints

Multi-phase models for timing closure of integrated circuit designs

Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designs

Method, system, and computer program product for implementing prototyping and floorplanning of electronic circuit designs

Methods, systems, and articles of manufacture for synchronous hierarchical implementation of electronic circuit designs

Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis

BHARDWAJ VIVEK

Methods for single pass parallel hierarchical timing closure of integrated circuit designs

Systems for single pass parallel hierarchical timing closure of integrated circuit designs

User interface for timing budget analysis of integrated circuit designs

Methods for generating a user interface for timing budget analysis of integrated circuit designs

SYNOPSYS INC

Black box transparency in a circuit timing model

Unified timing analysis for model interface layout parasitics

SINGH SUSHOBHIT

Common path pessimism removal for hierarchical timing analysis

GUPTA DINESH

Multi-phase models for timing closure of integrated circuit designs

ARORA SUMIT

Timing budgeting of nested partitions for hierarchical integrated circuit designs

CANDENCE DESGIN SYSTEMS INC

Method and system for implementing clock tree prototyping

CHANG HONGLIANG

System and method of computing pin criticalities under process variations for timing analysis and optimization

LIU DONGZI

Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design data

LEVITSKY OLEG

Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraints