Inventor
LOOI LILY P
US20 patents
⚠️ This page may combine multiple inventors who share the name “LOOI LILY P”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
17 patentsUS6615319B2Sep 2, 2003
Distributed mechanism for resolving cache coherence conflicts in a multi-node computer architecture
INTEL CORP95 citations97
US7234029B2Jun 19, 2007
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
INTEL CORP27 citations92
US7124252B1Oct 17, 2006
Method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system
INTEL CORP28 citations92
US6842830B2Jan 11, 2005
Mechanism for handling explicit writeback in a cache coherent multi-node architecture
INTEL CORP39 citations92
US6772298B2Aug 3, 2004
Method and apparatus for invalidating a cache line without data return in a multi-node architecture
INTEL CORP24 citations92
US6859864B2Feb 22, 2005
Mechanism for initiating an implicit write-back in response to a read or snoop of a modified cache line
INTEL CORP14 citations84
US7996625B2Aug 9, 2011
Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
INTEL CORP10 citations83
US7167957B2Jan 23, 2007
Mechanism for handling explicit writeback in a cache coherent multi-node architecture
INTEL CORP9 citations73
US9910814B2Mar 6, 2018
Method, apparatus and system for single-ended communication of transaction layer packets
INTEL CORP2 citations72
US6976129B2Dec 13, 2005
Mechanism for handling I/O transactions with known transaction length to coherent memory in a cache coherent multi-node architecture
INTEL CORP5 citations63
US7617329B2Nov 10, 2009
Programmable protocol to support coherent and non-coherent transactions in a multinode system
INTEL CORP6 citations62
US7383398B2Jun 3, 2008
Preselecting E/M line replacement technique for a snoop filter
INTEL CORP5 citations62
US6622215B2Sep 16, 2003
Mechanism for handling conflicts in a multi-node computer architecture
INTEL CORP4 citations62
US10949356B2Mar 16, 2021
Fast page fault handling process implemented on persistent memory
INTEL CORP0 citations59
US10496152B2Dec 3, 2019
Power control techniques for integrated PCIe controllers
INTEL CORP0 citations51
US9537665B2Jan 3, 2017
Method, apparatus, and system for enabling platform power states
INTEL CORP0 citations51
US11029744B2Jun 8, 2021
System, apparatus and method for controlling a processor based on effective stress information
INTEL CORP0 citations50