Inventor
VAKHARWALA RUPIN H
US16 patents
⚠️ This page may combine multiple inventors who share the name “VAKHARWALA RUPIN H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
15 patentsUS7370160B2May 6, 2008
Virtualizing memory type
INTEL CORP20 citations91
US10048881B2Aug 14, 2018
Restricted address translation to protect against device-TLB vulnerabilities
INTEL CORP10 citations84
US10970238B2Apr 6, 2021
Non-posted write transactions for a computer bus
INTEL CORP4 citations72
US9954792B2Apr 24, 2018
Shared flow control credits
INTEL CORP3 citations69
US12332813B2Jun 17, 2025
Non-posted write transactions for a computer bus
INTEL CORP0 citations62
US12210660B2Jan 28, 2025
Cryptographic computing with legacy peripheral devices
INTEL CORP0 citations62
US11726927B2Aug 15, 2023
Method, apparatus, system for early page granular hints from a PCIe device
INTEL CORP0 citations62
US11513979B2Nov 29, 2022
Non-posted write transactions for a computer bus
INTEL CORP0 citations62
US11347662B2May 31, 2022
Method, apparatus, system for early page granular hints from a PCIe device
INTEL CORP0 citations62
US10817447B2Oct 27, 2020
Input/output translation lookaside buffer (IOTLB) quality of service (QoS)
INTEL CORP1 citations59
US11126554B2Sep 21, 2021
Prefetching write permissions into address translation cache
INTEL CORP1 citations56
US10248574B2Apr 2, 2019
Input/output translation lookaside buffer prefetching
INTEL CORP1 citations56
US12498963B2Dec 16, 2025
User-level interrupts in virtual machines
INTEL CORP0 citations52
US10936490B2Mar 2, 2021
System and method for per-agent control and quality of service of shared resources in chip multiprocessor platforms
INTEL CORP0 citations52
US12326816B2Jun 10, 2025
Technologies for offload device fetching of address translations
INTEL CORP0 citations50