Inventor

CHIDAMBARAM PERIANNAN

US57 patents

⚠️ This page may combine multiple inventors who share the name “CHIDAMBARAM PERIANNAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHIDAMBARAM PERIANNAN

QUALCOMM INC

Programmable circuits for performing machine learning operations on edge devices

Three-dimensional (3D) integrated circuit device having a backside power delivery network

Capacitor interposer layer (CIL) in a die-to-wafer three-dimensional (3D) integrated circuit (IC) (3DIC)

Integrated circuit (IC) interconnect structure having a metal layer with asymmetric metal line-dielectric structures supporting self-aligned vertical interconnect accesses (VIAS)

Three-dimensional (3D), vertically-integrated field-effect transistors (FETs) for complementary metal-oxide semiconductor (CMOS) cell circuits

Compound semiconductor field effect transistor gate length scaling

Trench capacitor assembly for high capacitance density

Stacked decoupling capacitors with integration in a substrate

Device comprising contact to contact coupling of packages

Integrated circuit package with a magnetic core

Bulk acoustic wave (BAW) and passive-on-glass (POG) filter co-integration

Standard cell circuits employing high aspect ratio voltage rails for reduced resistance

Metal oxide semiconductor (MOS) isolation schemes with continuous active areas separated by dummy gates and related methods

Integrated circuit assembly with hybrid bonding

Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs)

Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate for interfacing an IC chip(s) to a package substrate, and related methods

Three-dimensional (3D) integrated circuit (IC) integration of an embedded chip and a preformed metal routing structure

Trench capacitor component with reduced equivalent series resistance and equivalent series inductance

Dynamic random-access memory (DRAM) on hot compute logic for last-level-cache

Integrated circuit assembly with hybrid bonding

Deep trench capacitors in an inter-layer medium on an interconnect layer of an integrated circuit die and related methods

Trench capacitor assembly for high capacitance density

MIM capacitor with adjustable capacitance via electronic fuses

Impedance matching transceiver

MIM capacitor with adjustable capacitance via electronic fuses

Integrated device coupled to a capacitor structure comprising a trench capacitor

CMOS integrated humidity sensor with built-in heater

Transistor devices with double-side contacts

Hybrid reconstituted substrate for electronic packaging

Substrate comprising an inductor and a capacitor located in an encapsulation layer

Artificial neural networks with precision weight for artificial intelligence

Package comprising stacked filters with a shared substrate cap

Multi-bit compute-in-memory (CIM) arrays employing bit cell circuits optimized for accuracy and power efficiency

Fast digital multiply-accumulate (MAC) by fast digital multiplication circuit

Compute-in-memory (CIM) binary multiplier

Voltage regulation integrated circuit (IC) with circuit components in an integrated three-dimensional (3D) inductor core and related methods of fabrication

High power compound semiconductor field effect transistor devices with low doped drain

Modified self-aligned quadruple patterning (SAQP) processes using cut pattern masks to fabricate integrated circuit (IC) cells with reduced area

TEXAS INSTRUMENTS INC

Fabrication of abrupt ultra-shallow junctions

Growth of unfaceted SiGe in MOS transistor fabrication

Recess etch for epitaxial SiGe

Integration scheme to improve NMOS with poly cap while mitigating PMOS degradation

Methodology of implementing ultra high temperature (UHT) anneal in fabricating devices that contain sige

Highly activated carbon selective epitaxial process for CMOS

Fabrication of abrupt ultra-shallow junctions

Method to improve performance of secondary active components in an esige CMOS technology

Semiconductor device made by multiple anneal of stress inducing layer

Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps

Fabrication of ultra shallow junctions from a solid source with fluorine implantation

Versatile system for limiting electric field degradation of semiconductor structures