Inventor
MATHEWS GREG S
US6 patents
Patents
6 patentsUS6728800B1Apr 27, 2004
Efficient performance based scheduling mechanism for handling multiple TLB operations
INTEL CORP224 citations93
US6675266B2Jan 6, 2004
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP11 citations81
US6904502B2Jun 7, 2005
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP4 citations73
US6775746B2Aug 10, 2004
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP4 citations73
US7315920B2Jan 1, 2008
Circuit and method for protecting vector tags in high performance microprocessors
INTEL CORP2 citations62
US6839814B2Jan 4, 2005
Circuit and method for protecting 1-hot and 2-hot vector tags in high performance microprocessors
INTEL CORP0 citations51