Inventor · disambiguated record
Michael R. Betker
Also filed as: BETKER MICHAEL · BETKER MICHAEL R · BETKER MICHAEL RICHARD
19 granted patents·1,104 citations·filing 1986–2012
96Inventor score
Files withLUCENT TECHNOLOGIES INC5AGERE SYSTEMS INC3BYRNE RICHARD J2LSI CORP2VOYAGER TECHNOLOGIES INC2
Top patents by PatentIndex Score
19 records- 0196US8255644B2Network communications processor architecture with memory load balancingSONNIER DAVID P·Filed 2010·Granted Aug 28, 2012·43 cites·12 claims
- 0296US6092186AApparatus and method for aborting un-needed instruction fetches in a digital microprocessor deviceLUCENT TECHNOLOGIES INC·Filed 1996·Granted Jul 18, 2000·429 cites·20 claims
- 0393US4757422ADynamically balanced ionization blowerVOYAGER TECHNOLOGIES INC·Filed 1986·Granted Jul 12, 1988·106 cites·27 claims
- 0491US8489792B2Transaction performance monitoring in a processor bus bridgeBYRNE RICHARD J·Filed 2010·Granted Jul 16, 2013·17 cites·20 claims
- 0590US8489794B2Processor bus bridge for network processors or the likeBYRNE RICHARD J·Filed 2010·Granted Jul 16, 2013·13 cites·33 claims
- 0687US8910168B2Task backpressure and deletion in a multi-flow network processor architectureLSI CORP·Filed 2012·Granted Dec 9, 2014·11 cites·20 claims
- 0787US5724505AApparatus and method for real-time program monitoring via a serial interfaceLUCENT TECHNOLOGIES INC·Filed 1996·Granted Mar 3, 1998·147 cites·28 claims
- 0883US4736157AWide-range resistance monitoring apparatus and methodVOYAGER TECHNOLOGIES INC·Filed 1986·Granted Apr 5, 1988·46 cites·11 claims
- 0982US8683221B2Configurable memory encryption with constant pipeline delay in a multi-core processorPEET JR CHARLES EDWARD·Filed 2011·Granted Mar 25, 2014·11 cites·18 claims
- 1080US6052766APointer register indirectly addressing a second register in the processor core of a digital processorLUCENT TECHNOLOGIES INC·Filed 1998·Granted Apr 18, 2000·103 cites·19 claims
- 1177US8539199B2Hash processing in a network communications processor architectureBURROUGHS WILLIAM·Filed 2011·Granted Sep 17, 2013·6 cites·20 claims
- 1274US7296259B2Processor system with cache-based software breakpointsAGERE SYSTEMS INC·Filed 2002·Granted Nov 13, 2007·22 cites·16 claims
- 1368US5909557AIntegrated circuit with programmable bus configurationLUCENT TECHNOLOGIES INC·Filed 1995·Granted Jun 1, 1999·57 cites·32 claims
- 1467US5889981AApparatus and method for decoding instructions marked with breakpoint codes to select breakpoint action from plurality of breakpoint actionsLUCENT TECHNOLOGIES INC·Filed 1996·Granted Mar 30, 1999·53 cites·32 claims
- 1565US7168067B2Multiprocessor system with cache-based software breakpointsAGERE SYSTEMS INC·Filed 2002·Granted Jan 23, 2007·12 cites·12 claims
- 1661US8873550B2Task queuing in a multi-flow network processor architectureLSI CORP·Filed 2012·Granted Oct 28, 2014·1 cites·20 claims
- 1760US7353513B2Method and apparatus for establishing a bound on the effect of task interference in a cache memoryAGERE SYSTEMS INC·Filed 2002·Granted Apr 1, 2008·6 cites·16 claims
- 1850US5577230AApparatus and method for computer processing using an enhanced Harvard architecture utilizing dual memory buses and the arbitration for data/instruction fetchAT & T CORP·Filed 1994·Granted Nov 19, 1996·21 cites·20 claims
- 1946US8191067B2Method and apparatus for establishing a bound on the effect of task interference in a cache memoryBETKER MICHAEL RICHARD·Filed 2008·Granted May 29, 2012·0 cites·12 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →