Inventor
SHAH LACKY V
US48 patents
⚠️ This page may combine multiple inventors who share the name “SHAH LACKY V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
NVIDIA CORP
20 patentsUS9710874B2Jul 18, 2017
Mid-primitive graphics execution preemption
NVIDIA CORP8 citations83
US9348762B2May 24, 2016
Technique for accessing content-addressable memory
NVIDIA CORP9 citations83
US10552201B2Feb 4, 2020
Software-assisted instruction level execution preemption
NVIDIA CORP3 citations72
US11579925B2Feb 14, 2023
Techniques for reconfiguring partitions in a parallel processing system
NVIDIA CORP3 citations71
US9678897B2Jun 13, 2017
Approach for context switching of lock-bit protected memory
NVIDIA CORP2 citations69
US12379959B2Aug 5, 2025
Compute task state encapsulation
NVIDIA CORP0 citations62
US12498979B2Dec 16, 2025
Techniques for configuring a processor to function as multiple, separate processors in a virtualized environment
NVIDIA CORP1 citations61
US10915364B2Feb 9, 2021
Technique for computational nested parallelism
NVIDIA CORP1 citations61
US11663036B2May 30, 2023
Techniques for configuring a processor to function as multiple, separate processors
NVIDIA CORP1 citations60
US11249905B2Feb 15, 2022
Techniques for configuring a processor to function as multiple, separate processors
NVIDIA CORP1 citations60
US9448837B2Sep 20, 2016
Cooperative thread array granularity context switch during trap handling
NVIDIA CORP2 citations60
US12443363B2Oct 14, 2025
High bandwidth extended memory in a parallel processing system
NVIDIA CORP0 citations58
US10552202B2Feb 4, 2020
Software-assisted instruction level execution preemption
NVIDIA CORP0 citations51
US9720858B2Aug 1, 2017
Technique for performing memory access operations via texture hardware
NVIDIA CORP0 citations51
US10095542B2Oct 9, 2018
Cooperative thread array granularity context switch during trap handling
NVIDIA CORP0 citations50
US9804885B2Oct 31, 2017
Cooperative thread array granularity context switch during trap handling
NVIDIA CORP0 citations50
US11893423B2Feb 6, 2024
Techniques for configuring a processor to function as multiple, separate processors
NVIDIA CORP0 citations49
US9697006B2Jul 4, 2017
Technique for performing memory access operations via texture hardware
NVIDIA CORP0 citations41
US10235208B2Mar 19, 2019
Technique for saving and restoring thread group operating state
NVIDIA CORP0 citations40
US10289418B2May 14, 2019
Cooperative thread array granularity context switch during trap handling
NVIDIA CORP0 citations39
HEWLETT PACKARD CO
12 patentsUS6205545B1Mar 20, 2001
Method and apparatus for using static branch predictions hints with dynamically translated code traces to improve performance
HEWLETT PACKARD CO190 citations99
US6115809ASep 5, 2000
Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction
HEWLETT PACKARD CO151 citations99
US6189141B1Feb 13, 2001
Control path evaluating trace designator with dynamically adjustable thresholds for activation of tracing for high (hot) activity and low (cold) activity of flow control
HEWLETT PACKARD CO279 citations98
US6164841ADec 26, 2000
Method, apparatus, and product for dynamic software code translation system
HEWLETT PACKARD CO155 citations98
US6327704B1Dec 4, 2001
System, method, and product for multi-branch backpatching in a dynamic translator
HEWLETT PACKARD CO79 citations96
US6295644B1Sep 25, 2001
Method and apparatus for patching program text to improve performance of applications
HEWLETT PACKARD CO65 citations96
US6223339B1Apr 24, 2001
System, method, and product for memory management in a dynamic translator
HEWLETT PACKARD CO69 citations96
US6148437ANov 14, 2000
System and method for jump-evaluated trace designation
HEWLETT PACKARD CO69 citations96
US5911073AJun 8, 1999
Method and apparatus for dynamic process monitoring through an ancillary control code system
HEWLETT PACKARD CO66 citations96
US6112280AAug 29, 2000
Method and apparatus for distinct instruction pointer storage in a partitioned cache memory
HEWLETT PACKARD CO35 citations92
US5721893AFeb 24, 1998
Exploiting untagged branch prediction cache by relocating branches
HEWLETT PACKARD CO35 citations92
US6052530AApr 18, 2000
Dynamic translation system and method for optimally translating computer code
HEWLETT PACKARD CO17 citations82
HEWLETT PACKARD DEVELOPMENT CO
3 patentsUS6622300B1Sep 16, 2003
Dynamic optimization of computer programs using code-rewriting kernal module
HEWLETT PACKARD DEVELOPMENT CO98 citations98
US6658486B2Dec 2, 2003
System and method for efficiently blocking event signals associated with an operating system
HEWLETT PACKARD DEVELOPMENT CO10 citations72
US7386861B2Jun 10, 2008
System and method for efficiently blocking event signals associated with an operating system
HEWLETT PACKARD DEVELOPMENT CO0 citations50