Inventor

HSU CHIN-CHANG

TW61 patents

⚠️ This page may combine multiple inventors who share the name “HSU CHIN-CHANG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU CHIN-CHANG

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-patterning conflict free integrated circuit design

Method and system of determining colorability of a layout

EDA tool and method for conflict detection during multi-patterning lithography

Triple-pattern lithography layout decomposition

Standard cell and semiconductor device including anchor nodes and method of making

Standard cell and semiconductor device including anchor nodes

Integrated circuit and method for manufacturing the same

Method of designing a semiconductor device, system for implementing the method and standard cell

EDA tool and method for conflict detection during multi-patterning lithography

Method of determining if layout design is N-colorable

Integrated circuit layout validation using machine learning

Integrated circuit layout validation using machine learning

Deterministic system for device layout optimization

Method of determining colorability of a semiconductor device and system for implementing the same

Multi-patterning graph reduction and checking flow method

Method of determining colorability of a semiconductor device and system for implementing the same

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes and method of making

Integrated circuit and system of manufacturing the same

Integrated circuit and method for manufacturing same

Integrated circuit layout validation using machine learning

Multi-patterning graph reduction and checking flow method

Multi-patterning graph reduction and checking flow method

Method and system for multi-patterning layout decomposition

Stretchable layout design for EUV defect mitigation

HSU CHIN-CHANG

Multi-patterning method

Methodology for analysis and fixing guidance of pre-coloring layout

Light emitting diode lead-frame

Decomposition and marking of semiconductor device design layout in double patterning lithography

Multi-patterning method

Light emitting diode lead-frame

Light emitting diode

Light emitting diode package

Light-emitting diode package including a cavity with a plurality of side-walls with different inclinations

TAIWAN SEMICONDUCTOR MFG

Conflict detection for self-aligned multiple patterning compliance

Triple-pattern lithography layout decomposition validation

Balancing mask loading

Self-aligned multiple patterning layout design

Conflict detection for self-aligned multiple patterning compliance

Multi-patterning method

Density gradient cell array

Density gradient cell array

LEXTAR ELECTRONICS CORP

Light-emitting diode package with roughened surface portions of the lead-frame

Light emitting diode packaging carrier

Light emitting diode packaging carrier

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

FU CHUNG-MIN

Recognition of template patterns with mask information

HSU FENG-JUNG

Light-emitting diode with metal structure and heat sink