Inventor

YANG Wen-ju

TW58 patents

⚠️ This page may combine multiple inventors who share the name “YANG Wen-ju”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YANG Wen-ju

TAIWAN SEMICONDUCTOR MFG CO LTD

Multi-patterning conflict free integrated circuit design

Method and system of determining colorability of a layout

Triple-pattern lithography layout decomposition

Standard cell and semiconductor device including anchor nodes and method of making

Standard cell and semiconductor device including anchor nodes

Integrated circuit and method for manufacturing the same

Method of designing a semiconductor device, system for implementing the method and standard cell

Method of determining if layout design is N-colorable

Integrated circuit layout validation using machine learning

Integrated circuit layout validation using machine learning

Method of determining colorability of a semiconductor device and system for implementing the same

Method of determining colorability of a semiconductor device and system for implementing the same

Boundary cell

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes

Integrated circuit device and method

Integrated circuit and method of manufacturing the same

Standard cell and semiconductor device including anchor nodes and method of making

Boundary cell

Integrated circuit and system of manufacturing the same

Integrated circuit and method for manufacturing same

Boundary cell

Integrated circuit layout validation using machine learning

Method and system for multi-patterning layout decomposition

Stretchable layout design for EUV defect mitigation

Triple-pattern lithography layout decomposition

Conflict detection for self-aligned multiple patterning compliance

Recognition of template patterns with mask information

TAIWAN SEMICONDUCTOR MFG

Stretch dummy cell insertion in FinFET process

Method of merging color sets of layout

Conflict detection for self-aligned multiple patterning compliance

Triple-pattern lithography layout decomposition validation

Balancing mask loading

Conflict detection for self-aligned multiple patterning compliance

In-phase grouping for voltage-dependent design rule

Multi-patterning method

Density gradient cell array

Stretch dummy cell insertion in FinFET process

Density gradient cell array

HSU CHIN-CHANG

Multi-patterning method

Methodology for analysis and fixing guidance of pre-coloring layout

Decomposition and marking of semiconductor device design layout in double patterning lithography

Multi-patterning method

SAE MAGNETICS HK LTD

Camera module

Camera module

Voice coil motor

LIN HUNG LUNG

Tool and method for eliminating multi-patterning conflicts

CHEN HUANG-YU

Routing system and method for double patterning technology

CHEN PI-TSUNG

Decomposing integrated circuit layout

FU CHUNG-MIN

Recognition of template patterns with mask information