Inventor

LIU JIN PING

US43 patents

⚠️ This page may combine multiple inventors who share the name “LIU JIN PING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LIU JIN PING

GLOBALFOUNDRIES INC

Integrated circuit having multiple threshold voltages

Liner and cap layer for placeholder source/drain contact structure planarization and replacement

Method for forming single diffusion breaks between finFET devices and the resulting devices

Methods for fabricating integrated circuits using self-aligned quadruple patterning

Integrated circuits including FINFET devices with shallow trench isolation that includes a thermal oxide layer and methods for making the same

Method for forming air gap structure using carbon-containing spacer

T-shaped fin isolation region and methods of fabrication

Fabricating fin structures with doped middle portions

Semiconductor device and methods of forming fins and gates with ultraviolet curing

Integrated circuits with relaxed silicon / germanium fins

Integration method for fabrication of metal gate based multiple threshold voltage devices and circuits

Replacement low-K spacer

Transistor structures and fabrication methods thereof

Method for reducing gate height variation due to overlapping masks

Facilitating fabricating gate-all-around nanowire field-effect transistors

Integrated circuits having laterally confined epitaxial material overlying fin structures and methods for fabricating same

Uniform gate height for mixed-type non-planar semiconductor devices

Containment structure for epitaxial growth in non-planar semiconductor structure

Conformal nitridation of one or more fin-type transistor layers

Devices and methods of forming finFETs with self aligned fin formation

Method of fabricating an interlayer structure of increased elasticity modulus

Transistor structures and fabrication methods thereof

Defect-free relaxed covering layer on semiconductor substrate with lattice mismatch

Methods of fabricating defect-free semiconductor structures

Conformal nitridation of one or more fin-type transistor layers

Devices comprising high-K dielectric layer and methods of forming same

Reducing liner corrosion during metallization of semiconductor devices

Integrated circuits and methods for fabricating integrated circuits with active area protection

Methods of fabricating integrated circuits

CHARTERED SEMICONDUCTOR MFG

Implant damage control by in-situ C doping during SiGe epitaxy for device applications

Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch

Integration for buried epitaxial stressor

Method of forming a relaxed semiconductor buffer layer on a substrate with a large lattice mismatch

Silicon-germanium virtual substrate and method of fabricating the same

Strained channel transistor structure and method

EDISON OPTO DONGGUAN CO LTD

Light emitting diode driving circuit

Light emitting diode driving circuit with low harmonic distortion

Light emitting diode driving circuit for reducing flicker effect

LIU JIN PING

Implant damage control by in-situ C doping during sige epitaxy for device applications

Integrated circuit system with carbon and non-carbon silicon

Strained channel transistor structure and method

GLOBAL FOUNDRIES INC

Devices and methods of forming bulk FinFETS with lateral seg for source and drain on dielectrics

GLOBALFOUNDRIES SG PTE LTD

Implant damage control by in-situ C doping during sige epitaxy for device applications