Inventor

NAVALE ADITYA

US84 patents

⚠️ This page may combine multiple inventors who share the name “NAVALE ADITYA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NAVALE ADITYA

INTEL CORP

Dynamic power control for reducing voltage level of graphics controller component of memory controller based on its degree of idleness

Power management for an integrated graphics device

Power/performance optimized memory controller considering processor power states

Dynamic cache and memory allocation for memory subsystems

Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness

Apparatus and method for memory address re-mapping of graphics data

Asynchronous execution mechanism

Hierarchical lossless compression and null data support

Dynamic power control for reduced voltage level of graphics controller component of memory controller based on its degree of idleness

Method and apparatus for dynamic DLL powerdown and memory self-refresh

Filter based throttling

Mid-thread pre-emption with software assisted context switch

Dynamic control of reduced voltage state of graphics controller component of memory controller

Dynamic control of reduced voltage state of graphics controller component of memory controller

System, apparatus and method for multi-die distributed memory mapped input/output support

Apparatus and method for scheduling graphics processing unit workloads from virtual machines

Efficient hardware mechanism to ensure shared resource data coherency across draw calls

Page management approach to fully utilize hardware caches for tiled rendering

System coherency in a distributed graphics processor hierarchy

Priority based context preemption

Method and apparatus for reordering memory requests for page coherency

Method and apparatus for deprioritizing a high priority client

Tile sequencing mechanism

Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system

Process synchronization between engines using data in a memory location

Apparatus and method for scalable error detection and reporting

Systems and methods in a graphics environment for providing shared virtual memory addressing support for a host system

Asynchronous execution mechanism

Workload scheduling and distribution on a distributed graphics device

Apparatus and method for scalable error detection and reporting

Range based flushing mechanism

Workload scheduling and distribution on a distributed graphics device

Apparatus and method for scalable error detection and reporting

Method and apparatus for reordering memory requests for page coherency

Method and apparatus for prioritizing a high priority client

Flexible partitioning of GPU resources

Multi-render partitioning

Compression using a flat mapping in virtual address space

Tile sequencing mechanism

Tile sequencing mechanism

Banking render cache for multiple access

VEMBU BALAJI

Memory address re-mapping of graphics data

Creating secure communication channels between processing elements

CPU independent graphics scheduler for performing scheduling operations for graphics hardware

Memory address re-mapping of graphics data

SAMSON ERIC C

Dynamic control of reduced voltage state of graphics controller component of memory controller

Dynamic control of reduced voltage state of graphics controller component of memory controller

KOKER ALTUG

Dynamic error handling using parity and redundant rows

SANKARAN RAJESH M

Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

SAMSON ERIC

Low power display mode