Inventor

JAMISON PAUL C

US53 patents

⚠️ This page may combine multiple inventors who share the name “JAMISON PAUL C”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JAMISON PAUL C

IBM

Method for forming metal replacement gate of high performance

Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures

High mobility FETS using A1203 as a gate oxide

Adhesion of silicon carbide films

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS

Controlling threshold voltage in nanosheet transistors

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Nitrogen-containing field effect transistor gate stack containing a threshold voltage control layer formed via deposition of a metal oxide

Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier

Thermally stable poly-Si/high dielectric constant material interfaces

Retrograde openings in thin films

Hard mask process to prevent surface roughness for selective dielectric etching

Low threshold voltage semiconductor device with dual threshold voltage control means

Method for improved plasma nitridation of ultra thin gate dielectrics

Method of forming metal/high-k gate stacks with high mobility

Oxide isolated fin-type field-effect transistors

Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials

Low threshold voltage semiconductor device with dual threshold voltage control means

Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices

Leakage current reduction in stacked metal-insulator-metal capacitors

Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices

Complementary metal oxide semiconductor replacement gate high-K metal gate devices with work function adjustments

Controlling threshold voltage in nanosheet transistors

Uniform threshold voltage for nanosheet devices

Leakage current reduction in stacked metal-insulator-metal capacitors

Controlling threshold voltage in nanosheet transistors

Stratified gate dielectric stack for gate dielectric leakage reduction

Fin field effect transistors having a nitride containing spacer to reduce lateral growth of epitaxially deposited semiconductor materials

Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier

Nitrided ultra thin gate dielectrics

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

Oxide isolated fin-type field-effect transistors

Surface area enhancement for stacked metal-insulator-metal (MIM) capacitor

Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement

Uniform threshold voltage for nanosheet devices

Stratified gate dielectric stack for gate dielectric leakage reduction

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Complementary metal oxide semiconductor replacement gate high-k metal gate devices with work function adjustments

Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETs

Leakage current reduction in stacked metal-insulator-metal capacitors

Leakage current reduction in stacked metal-insulator-metal capacitors

Multi-layer work function metal gates with similar gate thickness to achieve multi-VT for VFETs

Multilayer dielectric for metal-insulator-metal capacitor (MIMCAP) capacitance and leakage improvement

Approach to control over-etching of bottom spacers in vertical fin field effect transistor devices

JAGANNATHAN HEMANTH

Stratified gate dielectric stack for gate dielectric leakage reduction

Structure and method to obtain EOT scaled dielectric stacks

Structure and method to obtain EOT scaled dielectric stacks

TOKYO ELECTRON LTD

Method for controlling the forming voltage in resistive random access memory devices

Method for controlling the forming voltage in resistive random access memory devices

INFINEON TECHNOLOGIES AG

Modification of the wet characteristics of deposited layers and in-line control