Inventor

FAYRUSHIN ALBERT

US35 patents

⚠️ This page may combine multiple inventors who share the name “FAYRUSHIN ALBERT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FAYRUSHIN ALBERT

MICRON TECHNOLOGY INC

Select gate gate-induced-drain-leakage enhancement

Memory cells and arrays of elevationally-extending strings of memory cells

Microelectronic devices with dopant extensions near a GIDL region below a tier stack, and related methods and systems

Programmable charge-storage transistor, an array of elevationally-extending strings of memory cells, and a method of forming an array of elevationally-extending strings of memory cells

Sequential voltage ramp-down of access lines of non-volatile memory device

Sequential voltage ramp-down of access lines of non-volatile memory device

Apparatuses including band offset materials, and related systems

Semiconductor pillars having triangular-shaped lateral peripheries, and integrated assemblies

Back gates and related apparatuses, systems, and methods

Microelectronic devices, electronic systems, and related methods

Microelectronic devices with source region vertical extension between upper and lower channel regions, and related methods

Memory device having memory cell strings and separate read and write control gates

Microelectronic devices including isolation structures protruding into upper pillar portions, and related methods and systems

Sequential voltage ramp-down of access lines of non-volatile memory device

Select gate gate-induced-drain-leakage enhancement

Programmable charge-storage transistor, an array of elevationally-extending strings of memory cells, and a method of forming an array of elevationally-extending strings of memory cells

Microelectronic devices including isolation structures protruding into upper pillar portions, and related methods and systems

Back gates and related apparatuses, systems, and methods

Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods

Semiconductor pillars having triangular-shaped lateral peripheries, and integrated assemblies

NAND structures with polarized materials

Select gate transistor with segmented channel fin

Integrated assemblies, and methods of forming integrated assemblies

Integrated memory having the body region comprising a different semiconductor composition than the source/drain region

Microelectronic devices with vertically recessed channel structures and discrete, spaced inter-slit structures, and related methods and systems

SAMSUNG ELECTRONICS CO LTD

Methods of reading data from non-volatile semiconductor memory device

Semiconductor memory devices and methods of manufacturing the same

Methods of manufacturing semiconductor memory devices

Non-volatile memory devices having reduced susceptibility to leakage of stored charges

LODESTAR LICENSING GROUP LLC

Microelectronic devices including pillars with partially-circular upper portions and circular lower portions, and related methods

Apparatuses including band offset materials, and related memory devices

Integrated assemblies, and methods of forming integrated assemblies

Integrated assemblies, and methods of forming integrated assemblies

LEE CHANG-HYUN

Memory devices having semiconductor patterns on a substrate and methods of manufacturing the same

LEE JAEDUK

Non-volatile memory devices having a floating gate cap between a floating gate and a gate insulating layer