Inventor

VOLPE THOMAS A

US132 patents

⚠️ This page may combine multiple inventors who share the name “VOLPE THOMAS A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VOLPE THOMAS A

AMAZON TECH INC

Restructuring a multi-dimensional array

Pipelined evaluations for algorithmic forwarding route lookup

Execution synchronization and tracking

Instruction memory

Multiple accumulate busses in a systolic array

Tracking persistent memory usage

Reducing dynamic power consumption in arrays

Collecting statistics for persistent memory

Integrated packet generator and checker

Testing computer networks in real time

Efficient memory management in multi-tenant virtualized environment

Combined cache-overflow memory structure

Unified quality of service (QoS) for label switching traffic

Distributed precision time architecture

Non-recirculating label switching packet processing

Streaming interconnect architecture

Address translation and address translation memory for storage class memory

Page table search engine

Network packet tracing

Sampling based on large flow detection for network visibility monitoring

Large flow detection for network visibility monitoring

Performance monitoring for storage-class memory

Systolic array component combining multiple integer and floating-point data types

On-circuit data activity monitoring for a systolic array

Event-based device performance monitoring

Parallelism within a systolic array using multiple accumulate busses

Multiple busses in a grouped systolic array

Generating network packet centric signatures

Performance debug for networks

Network device with integrated packet generators or packet checkers

Filtering control plane decision requests for forwarding network packets

Write minimization for de-allocated memory

Uniform memory access architecture

Reliable precision time architecture

Robust fast re-routing for label switching packets

Congestion control for label switching traffic

Increasing positive clock skew for systolic array critical path

Tracking persistent memory usage

Memory mapping in an access device for non-volatile memory

Notifications in integrated circuits

Indexing a memory region

Multiple busses within a systolic array processing element

III HOLDINGS 2 LLC

Network proxy for high-performance, low-power data center interconnect fabric

System and method for data center security enhancements leveraging server SOCs or server fabrics

Network proxy for high-performance, low-power data center interconnect fabric

System and method for data center security enhancements leveraging managed server SOCs

System and method for data center security enhancements leveraging server SOCs or server fabrics

System and method for data center security enhancements leveraging managed server SOCs

Remote memory ring buffers in a cluster of data processing nodes

ANALOG DEVICES INC

Prefetch buffer method and apparatus