Inventor
ELMER THOMAS
US33 patents
⚠️ This page may combine multiple inventors who share the name “ELMER THOMAS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
AMAZON TECH INC
18 patentsUS10678508B2Jun 9, 2020
Accelerated quantized multiply-and-add operations
AMAZON TECH INC54 citations97
US11308027B1Apr 19, 2022
Multiple accumulate busses in a systolic array
AMAZON TECH INC15 citations94
US10817260B1Oct 27, 2020
Reducing dynamic power consumption in arrays
AMAZON TECH INC46 citations94
US11816446B2Nov 14, 2023
Systolic array component combining multiple integer and floating-point data types
AMAZON TECH INC7 citations86
US11467806B2Oct 11, 2022
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
AMAZON TECH INC10 citations86
US11232062B1Jan 25, 2022
Parallelism within a systolic array using multiple accumulate busses
AMAZON TECH INC16 citations86
US11423313B1Aug 23, 2022
Configurable function approximation based on switching mapping table content
AMAZON TECH INC13 citations85
US11422773B1Aug 23, 2022
Multiple busses within a systolic array processing element
AMAZON TECH INC17 citations84
US10983754B2Apr 20, 2021
Accelerated quantized multiply-and-add operations
AMAZON TECH INC5 citations84
US11308026B1Apr 19, 2022
Multiple busses interleaved in a systolic array
AMAZON TECH INC16 citations80
US11842169B1Dec 12, 2023
Systolic multiply delayed accumulate processor architecture
AMAZON TECH INC6 citations75
US11762803B2Sep 19, 2023
Multiple accumulate busses in a systolic array
AMAZON TECH INC4 citations75
US12182064B2Dec 31, 2024
Multiple accumulate busses in a systolic array
AMAZON TECH INC2 citations73
US12067375B2Aug 20, 2024
Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
AMAZON TECH INC2 citations73
US11880682B2Jan 23, 2024
Systolic array with efficient input reduction and extended array performance
AMAZON TECH INC5 citations73
US12423058B2Sep 23, 2025
Systolic array with input reduction to multiple reduced inputs
AMAZON TECH INC1 citations63
US12517700B1Jan 6, 2026
Systolic array with output rounding for multiple source/destination data type pairs
AMAZON TECH INC0 citations52
US12182691B1Dec 31, 2024
Increasing performance of computational array accelerators
AMAZON TECH INC0 citations50
VIA ALLIANCE SEMICONDUCTOR CO LTD
9 patentsUS9798519B2Oct 24, 2017
Standard format intermediate result
VIA ALLIANCE SEMICONDUCTOR CO LTD4 citations84
US9778907B2Oct 3, 2017
Non-atomic split-path fused multiply-accumulate
VIA ALLIANCE SEMICONDUCTOR CO LTD3 citations84
US9778908B2Oct 3, 2017
Temporally split fused multiply-accumulate operation
VIA ALLIANCE SEMICONDUCTOR CO LTD4 citations84
US10078512B2Sep 18, 2018
Processing denormal numbers in FMA hardware
VIA ALLIANCE SEMICONDUCTOR CO LTD3 citations73
US9891887B2Feb 13, 2018
Subdivision of a fused compound arithmetic operation
VIA ALLIANCE SEMICONDUCTOR CO LTD2 citations73
US10019230B2Jul 10, 2018
Calculation control indicator cache
VIA ALLIANCE SEMICONDUCTOR CO LTD1 citations63
US10019229B2Jul 10, 2018
Calculation control indicator cache
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US9891886B2Feb 13, 2018
Split-path heuristic for performing a fused FMA operation
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations52
US11061672B2Jul 13, 2021
Chained split execution of fused compound arithmetic operations
VIA ALLIANCE SEMICONDUCTOR CO LTD0 citations43