Inventor
FIRU DANIEL
US16 patents
⚠️ This page may combine multiple inventors who share the name “FIRU DANIEL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
21 INC
8 patentsUS10839378B1Nov 17, 2020
Systems and methods for performing device authentication operations using cryptocurrency transactions
21 INC27 citations90
US11270298B2Mar 8, 2022
Digital currency mining circuitry
21 INC8 citations81
US9942046B2Apr 10, 2018
Digital currency mining circuitry with adaptable difficulty compare capabilities
21 INC4 citations72
US9659123B2May 23, 2017
Systems and methods for flexibly optimizing processing circuit efficiency
21 INC2 citations72
US11301481B2Apr 12, 2022
Digital currency mining circuitry having shared processing logic
21 INC1 citations61
US10409827B2Sep 10, 2019
Digital currency mining circuitry having shared processing logic
21 INC1 citations61
US10338558B2Jul 2, 2019
Sequential logic circuitry with reduced dynamic power consumption
21 INC1 citations61
US10558188B2Feb 11, 2020
Sequential logic circuitry with reduced dynamic power consumption
21 INC0 citations51
QUADRIC IO INC
6 patentsUS11755806B2Sep 12, 2023
Systems and methods for executing a programmable finite state machine that accelerates fetchless computations and operations of an array of processing cores of an integrated circuit
QUADRIC IO INC1 citations61
US11087067B2Aug 10, 2021
Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit
QUADRIC IO INC1 citations61
US10761848B1Sep 1, 2020
Systems and methods for implementing core level predication within a machine perception and dense algorithm integrated circuit
QUADRIC IO INC1 citations61
US11392667B2Jul 19, 2022
Systems and methods for an intelligent mapping of neural network weights and input data to an array of processing cores of an integrated circuit
QUADRIC IO INC0 citations51
US11714556B2Aug 1, 2023
Systems and methods for accelerating memory transfers and computation efficiency using a computation-informed partitioning of an on-chip data buffer and implementing computation-aware data transfer operations to the on-chip data buffer
QUADRIC IO INC0 citations50
US11061678B1Jul 13, 2021
Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit
QUADRIC IO INC0 citations47